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/openbmc/linux/drivers/net/ethernet/mediatek/
H A Dmtk_ppe.c26 static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val) in ppe_w32() argument
28 writel(val, ppe->base + reg); in ppe_w32()
31 static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg) in ppe_r32() argument
33 return readl(ppe->base + reg); in ppe_r32()
36 static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set) in ppe_m32() argument
40 val = ppe_r32(ppe, reg); in ppe_m32()
43 ppe_w32(ppe, reg, val); in ppe_m32()
48 static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val) in ppe_set() argument
50 return ppe_m32(ppe, reg, 0, val); in ppe_set()
53 static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val) in ppe_clear() argument
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H A Dmtk_ppe.h349 void mtk_ppe_start(struct mtk_ppe *ppe);
350 int mtk_ppe_stop(struct mtk_ppe *ppe);
351 int mtk_ppe_prepare_reset(struct mtk_ppe *ppe);
353 void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash);
356 mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash) in mtk_ppe_check_skb() argument
360 if (!ppe) in mtk_ppe_check_skb()
367 diff = now - ppe->foe_check_time[hash]; in mtk_ppe_check_skb()
371 ppe->foe_check_time[hash] = now; in mtk_ppe_check_skb()
372 __mtk_ppe_check_skb(ppe, skb, hash); in mtk_ppe_check_skb()
398 int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
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H A Dmtk_ppe_debugfs.c78 struct mtk_ppe *ppe = m->private; in mtk_ppe_debugfs_foe_show() local
82 struct mtk_foe_entry *entry = mtk_foe_get_entry(ppe, i); in mtk_ppe_debugfs_foe_show()
99 acct = mtk_foe_entry_get_mib(ppe, i, NULL); in mtk_ppe_debugfs_foe_show()
101 type = mtk_get_ib1_pkt_type(ppe->eth, entry->ib1); in mtk_ppe_debugfs_foe_show()
183 int mtk_ppe_debugfs_init(struct mtk_ppe *ppe, int index) in mtk_ppe_debugfs_init() argument
187 snprintf(ppe->dirname, sizeof(ppe->dirname), "ppe%d", index); in mtk_ppe_debugfs_init()
189 root = debugfs_create_dir(ppe->dirname, NULL); in mtk_ppe_debugfs_init()
190 debugfs_create_file("entries", S_IRUGO, root, ppe, &mtk_ppe_debugfs_foe_all_fops); in mtk_ppe_debugfs_init()
191 debugfs_create_file("bind", S_IRUGO, root, ppe, &mtk_ppe_debugfs_foe_bind_fops); in mtk_ppe_debugfs_init()
H A Dmtk_ppe_offload.c460 err = mtk_foe_entry_commit(eth->ppe[entry->ppe_index], entry); in mtk_flow_offload_replace()
472 mtk_foe_entry_clear(eth->ppe[entry->ppe_index], entry); in mtk_flow_offload_replace()
490 mtk_foe_entry_clear(eth->ppe[entry->ppe_index], entry); in mtk_flow_offload_destroy()
512 idle = mtk_foe_entry_idle_time(eth->ppe[entry->ppe_index], entry); in mtk_flow_offload_stats()
516 mtk_foe_entry_get_mib(eth->ppe[entry->ppe_index], entry->hash, in mtk_flow_offload_stats()
/openbmc/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_ppe.c64 * hns_ppe_common_get_cfg - get ppe common config
142 * hns_ppe_checksum_hw - set ppe checksum caculate
143 * @ppe_cb: ppe device
161 * hns_ppe_set_qid - set ppe qid
162 * @ppe_common: ppe common device
179 * @ppe_cb: ppe device
189 * hns_ppe_common_init_hw - init ppe common device
190 * @ppe_common: ppe common device
240 "get ppe queue mode failed! dsaf_mode=%d\n", in hns_ppe_common_init_hw()
253 /*clr ppe exception irq*/
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H A Dhns_dsaf_ppe.h74 struct hns_ppe_cb *next; /* pointer to next ppe device */
78 u8 index; /* index in a ppe common device */
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hip04-net.txt10 phandle, specifies a reference to the syscon ppe node
22 * Ethernet ppe node:
28 - compatible: "hisilicon,hip04-ppe", "syscon".
60 ppe: ppe@28c0000 {
61 compatible = "hisilicon,hip04-ppe", "syscon";
70 port-handle = <&ppe 31 0 31>;
78 port-handle = <&ppe 0 1 0>;
87 port-handle = <&ppe 8 2 8>;
H A Dhisilicon-hns-dsaf.txt20 The third region is the PPE register base and size.
23 - reg-names: may be ppe-base and(or) dsaf-base. It is used to find the
64 reg-names = "ppe-base", "dsaf-base";
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dmac.h412 * enum iwl_he_pkt_ext_constellations - PPE constellation indices
439 * The required PPE is set via HE Capabilities IE, per Nss x BW x MCS
446 * QAM_tx < QAM_th1 --> PPE=0us
447 * QAM_th1 <= QAM_tx < QAM_th2 --> PPE=8us
448 * QAM_th2 <= QAM_tx --> PPE=16us
451 * For rates below the low_th, no need for PPE
452 * For rates between low_th and high_th, need 8us PPE
453 * For rates equal or higher then the high_th, need 16us PPE
463 * The required PPE is set via HE Capabilities IE, per Nss x BW x MCS
470 * QAM_tx < QAM_th1 --> PPE=0us
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/openbmc/qemu/util/
H A Dmain-loop.c330 PollingEntry **ppe, *pe;
334 for(ppe = &first_polling_entry; *ppe != NULL; ppe = &(*ppe)->next);
335 *ppe = pe;
341 PollingEntry **ppe, *pe;
342 for(ppe = &first_polling_entry; *ppe != NULL; ppe = &(*ppe)->next) {
343 pe = *ppe;
345 *ppe = pe->next;
/openbmc/linux/arch/powerpc/platforms/cell/
H A Dcbe_thermal.c187 /* shows the temperature of the DTS on the PPE,
195 /* shows the temperature of the second DTS on the PPE */
272 static DEVICE_PREFIX_ATTR(ppe, throttle_end, 0600);
273 static DEVICE_PREFIX_ATTR(ppe, throttle_begin, 0600);
274 static DEVICE_PREFIX_ATTR(ppe, throttle_full_stop, 0600);
305 /* ppe in init_default_values()
309 tpr.ppe = 0x1F0803; in init_default_values()
/openbmc/linux/drivers/ata/
H A Dpata_sch.c34 PPE = (1 << 30), /* Prefetch/Post Enable */ enumerator
106 data &= ~(PM | PPE); in sch_set_piomode()
108 /* enable PPE for block device */ in sch_set_piomode()
110 data |= PPE; in sch_set_piomode()
H A Dpata_oldpiix.c92 control |= 4; /* PPE */ in oldpiix_set_piomode()
97 * Set PPE, IE and TIME as appropriate. in oldpiix_set_piomode()
141 * IORDY unconditionally along with TIME1. PPE has already in oldpiix_set_dmamode()
155 /* Intel specifies that the PPE functionality is for disk only */ in oldpiix_set_dmamode()
157 control |= 4; /* PPE enable */ in oldpiix_set_dmamode()
H A Dpata_mpiix.c43 PPE = (1 << 2), enumerator
91 /* Mask the IORDY/TIME/PPE for this device */ in mpiix_set_piomode()
93 control |= PPE; /* Enable prefetch/posting for disk */ in mpiix_set_piomode()
H A Dpata_efar.c112 control |= 4; /* PPE */ in efar_set_piomode()
118 /* Set PPE, IE, and TIME as appropriate */ in efar_set_piomode()
194 * IORDY unconditionally along with TIME1. PPE has already in efar_set_dmamode()
H A Dpata_it8213.c101 control |= 4; /* PPE */ in it8213_set_piomode()
105 /* Set PPE, IE, and TIME as appropriate */ in it8213_set_piomode()
189 * IORDY unconditionally along with TIME1. PPE has already in it8213_set_dmamode()
H A Dpata_rdc.c114 control |= 4; /* PPE enable */ in rdc_set_piomode()
138 /* Enable PPE, IE and TIME as appropriate */ in rdc_set_piomode()
229 * IORDY unconditionally along with TIME1. PPE has already in rdc_set_dmamode()
/openbmc/linux/block/partitions/
H A Daix.c50 struct ppe { struct
64 struct ppe ppe[1016]; argument
232 struct ppe *p = pvd->ppe + i; in aix_partition()
/openbmc/linux/drivers/media/platform/nvidia/tegra-vde/
H A Dvde.h99 void __iomem *ppe; member
218 if (vde->ppe == base) in tegra_vde_reg_base_name()
219 return "PPE"; in tegra_vde_reg_base_name()
H A Dvde.c251 vde->ppe = devm_platform_ioremap_resource_byname(pdev, "ppe"); in tegra_vde_probe()
252 if (IS_ERR(vde->ppe)) in tegra_vde_probe()
253 return PTR_ERR(vde->ppe); in tegra_vde_probe()
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dnvidia,tegra-vde.yaml36 - const: ppe
106 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
/openbmc/linux/drivers/net/wireless/ath/ath12k/
H A Drx_desc.h214 * as PPE may not support such packets.
220 * Global enable/disable bit for routing to PPE, used to disable
221 * PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE'
224 * buffer management for WiFi-to-PPE routing.
227 * by a different subsystem, completely disabling WiFi-to-PPE
550 * Opaque service code between PPE and Wi-Fi
551 * This field gets passed on by REO to PPE in the EDMA descriptor
555 * This field gets passed on by REO to PPE in the EDMA descriptor
561 * This field gets passed on by REO to PPE in the EDMA descriptor
1014 * Opaque service code between PPE and Wi-Fi
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/openbmc/linux/arch/mips/lantiq/
H A Dclk.c30 unsigned long io, unsigned long ppe) in clkdev_add_static() argument
35 cpu_clk_generic[3].rate = ppe; in clkdev_add_static()
/openbmc/linux/arch/powerpc/platforms/cell/spufs/
H A Dspu_restore.c182 * here by the PPE Sequence for SPU Context in restore_complete()
285 * 1. The EA for LSCSA is passed from PPE in the
288 * into LS, rather than pushed by PPE.
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Dmac80211.c1993 static u8 iwl_mvm_he_get_ppe_val(u8 *ppe, u8 ppe_pos_bit) in iwl_mvm_he_get_ppe_val() argument
2001 return (ppe[byte_num] >> bit_num) & in iwl_mvm_he_get_ppe_val()
2012 res = (ppe[byte_num + 1] & in iwl_mvm_he_get_ppe_val()
2015 res += (ppe[byte_num] >> bit_num) & (BIT(residue_bits) - 1); in iwl_mvm_he_get_ppe_val()
2022 u8 ru_index_bitmap, u8 *ppe, u8 ppe_pos_bit, in iwl_mvm_parse_ppe() argument
2050 * According to the 11be spec, if for a specific BW the PPE Thresholds in iwl_mvm_parse_ppe()
2052 * BW for which we had PPE Thresholds. In 11ax though, we don't have in iwl_mvm_parse_ppe()
2062 high_th = iwl_mvm_he_get_ppe_val(ppe, ppe_pos_bit); in iwl_mvm_parse_ppe()
2064 low_th = iwl_mvm_he_get_ppe_val(ppe, ppe_pos_bit); in iwl_mvm_parse_ppe()
2081 u8 *ppe = &link_sta->he_cap.ppe_thres[0]; in iwl_mvm_set_pkt_ext_from_he_ppe() local
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