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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A DKconfig246 default "fsl,ls1012a-pcie" if ARCH_LS1012A
247 default "fsl,ls1043a-pcie" if ARCH_LS1043A
248 default "fsl,ls1046a-pcie" if ARCH_LS1046A
249 default "fsl,ls2080a-pcie" if ARCH_LS2080A
250 default "fsl,ls1088a-pcie" if ARCH_LS1088A
251 default "fsl,lx2160a-pcie" if ARCH_LX2160A
287 stage instead of the RAM version of U-Boot. Once PPA is initialized,
288 the rest of U-Boot (including RAM version) runs at EL2.
290 prompt "FSL Layerscape PPA firmware loading-media select"
315 hex "Length of PPA ESBC header"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soundwire/
H A Dqcom,soundwire.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - qcom,soundwire-v1.3.0
20 - qcom,soundwire-v1.5.0
21 - qcom,soundwire-v1.5.1
22 - qcom,soundwire-v1.6.0
23 - qcom,soundwire-v1.7.0
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/openbmc/linux/tools/testing/selftests/bpf/progs/
H A Dtest_l4lb_noinline.c1 // SPDX-License-Identifier: GPL-2.0
20 static __always_inline __u32 rol32(__u32 word, unsigned int shift) in rol32() argument
22 return (word << shift) | (word >> ((-shift) & 31)); in rol32()
30 a -= c; a ^= rol32(c, 4); c += b; \
31 b -= a; b ^= rol32(a, 6); a += c; \
32 c -= b; c ^= rol32(b, 8); b += a; \
33 a -= c; a ^= rol32(c, 16); c += b; \
34 b -= a; b ^= rol32(a, 19); a += c; \
35 c -= b; c ^= rol32(b, 4); b += a; \
40 c ^= b; c -= rol32(b, 14); \
[all …]
H A Dtest_l4lb.c24 static inline __u32 rol32(__u32 word, unsigned int shift) in rol32() argument
26 return (word << shift) | (word >> ((-shift) & 31)); in rol32()
34 a -= c; a ^= rol32(c, 4); c += b; \
35 b -= a; b ^= rol32(a, 6); a += c; \
36 c -= b; c ^= rol32(b, 8); b += a; \
37 a -= c; a ^= rol32(c, 16); c += b; \
38 b -= a; b ^= rol32(a, 19); a += c; \
39 c -= b; c ^= rol32(b, 4); b += a; \
44 c ^= b; c -= rol32(b, 14); \
45 a ^= c; a -= rol32(c, 11); \
[all …]
H A Dtest_l4lb_noinline_dynptr.c1 // SPDX-License-Identifier: GPL-2.0
22 static __always_inline __u32 rol32(__u32 word, unsigned int shift) in rol32() argument
24 return (word << shift) | (word >> ((-shift) & 31)); in rol32()
32 a -= c; a ^= rol32(c, 4); c += b; \
33 b -= a; b ^= rol32(a, 6); a += c; \
34 c -= b; c ^= rol32(b, 8); b += a; \
35 a -= c; a ^= rol32(c, 16); c += b; \
36 b -= a; b ^= rol32(a, 19); a += c; \
37 c -= b; c ^= rol32(b, 4); b += a; \
42 c ^= b; c -= rol32(b, 14); \
[all …]
H A Dtest_xdp_noinline.c1 // SPDX-License-Identifier: GPL-2.0
19 static __always_inline __u32 rol32(__u32 word, unsigned int shift) in rol32() argument
21 return (word << shift) | (word >> ((-shift) & 31)); in rol32()
29 a -= c; a ^= rol32(c, 4); c += b; \
30 b -= a; b ^= rol32(a, 6); a += c; \
31 c -= b; c ^= rol32(b, 8); b += a; \
32 a -= c; a ^= rol32(c, 16); c += b; \
33 b -= a; b ^= rol32(a, 19); a += c; \
34 c -= b; c ^= rol32(b, 4); b += a; \
39 c ^= b; c -= rol32(b, 14); \
[all …]
/openbmc/linux/drivers/tty/
H A Dmoxa.c1 // SPDX-License-Identifier: GPL-2.0+
4 * moxa.c -- MOXA Intellio family multiport serial driver.
6 * Copyright (C) 1999-2000 Moxa Technologies (support@moxa.com).
68 #define C218_key (C218_ConfBase + 4) /* WORD (0x218 for C218) */
69 #define C218DLoad_len (C218_ConfBase + 6) /* WORD */
72 #define C218_TestRx (C218_ConfBase + 0x10) /* 8 bytes for 8 ports */
73 #define C218_TestTx (C218_ConfBase + 0x18) /* 8 bytes for 8 ports */
74 #define C218_RXerr (C218_ConfBase + 0x20) /* 8 bytes for 8 ports */
75 #define C218_ErrFlag (C218_ConfBase + 0x28) /* 8 bytes for 8 ports */
90 #define C320_key C320_ConfBase + 4 /* WORD (0320H for C320) */
[all …]
/openbmc/linux/arch/mips/lantiq/xway/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
44 #define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */
45 #define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */
46 #define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */
66 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_enable_irq()
67 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); in ltq_dma_enable_irq()
78 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_disable_irq()
79 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); in ltq_dma_disable_irq()
90 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_ack_irq()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dnvm.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000_raise_eec_clk - Raise EEPROM clock
18 udelay(hw->nvm.delay_usec); in e1000_raise_eec_clk()
22 * e1000_lower_eec_clk - Lower EEPROM clock
33 udelay(hw->nvm.delay_usec); in e1000_lower_eec_clk()
37 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
48 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_shift_out_eec_bits()
52 mask = BIT(count - 1); in e1000_shift_out_eec_bits()
53 if (nvm->type == e1000_nvm_eeprom_spi) in e1000_shift_out_eec_bits()
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/openbmc/linux/arch/alpha/include/asm/
H A Dcore_cia.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
25 * EC-QE18B-TE
36 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
38 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
40 * | Byte Enable --+ |
41 * | Transfer Length --+
42 * +-- IO space, not cached
45 * Enable Length Transfer Byte Address
46 * adr<6:5> adr<4:3> Length Enable Adder
[all …]
/openbmc/linux/drivers/infiniband/hw/qib/
H A Dqib_common.h16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 /* This is the IEEE-assigned OUI for QLogic Inc. QLogic_IB */
123 * open to get implementation-specific info, and info specific to this
146 * than this (in words). Included is the starting control word, so
162 /* per-chip and other runtime features bitmap (QIB_RUNTIME_*) */
295 * The high bit is 0 for non-QLogic and 1 for QLogic-built/supplied.
319 * across ports and HCAs, using different algorithims. WITHIN is
323 * ports; this is the default */
325 * active ports within), then next HCA */
[all …]
/openbmc/linux/drivers/usb/serial/
H A Dmct_u232.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Definitions for MCT (Magic Control Technology) USB-RS232 Converter Driver
7 * This driver is for the device MCT USB-RS232 Converter (25 pin, Model No.
8 * U232-P25) from Magic Control Technology Corp. (there is also a 9 pin
9 * Model No. U232-P9). See http://www.mct.com.tw/products/product_us232.html
11 * of this file. This device was used in the Dlink DSB-S25.
24 /* U232-P25, Sitecom */
27 /* DU-H3SP USB BAY hub */
28 #define MCT_U232_DU_H3SP_PID 0x0200 /* D-Link DU-H3SP USB BAY */
30 /* Belkin badge the MCT U232-P9 as the F5U109 */
[all …]
/openbmc/qemu/hw/net/
H A De1000_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
37 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
38 #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */
39 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
40 #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */
41 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
42 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
43 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_nvm.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
11 * igb_raise_eec_clk - Raise EEPROM clock
22 udelay(hw->nvm.delay_usec); in igb_raise_eec_clk()
26 * igb_lower_eec_clk - Lower EEPROM clock
37 udelay(hw->nvm.delay_usec); in igb_lower_eec_clk()
41 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM
52 struct e1000_nvm_info *nvm = &hw->nvm; in igb_shift_out_eec_bits()
56 mask = 1u << (count - 1); in igb_shift_out_eec_bits()
57 if (nvm->type == e1000_nvm_eeprom_spi) in igb_shift_out_eec_bits()
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
47 * - only on 75x/76x
50 * - only on 75x/76x
53 * - only on 75x/76x
56 * - only on 75x/76x
70 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_main.c1 // SPDX-License-Identifier: GPL-2.0+
25 #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3))
30 { .compatible = "microchip,lan966x-switch" },
83 dev_err(&pdev->dev, "Invalid resource\n"); in lan966x_create_targets()
84 return -EINVAL; in lan966x_create_targets()
87 begin[idx] = devm_ioremap(&pdev->dev, in lan966x_create_targets()
88 iores[idx]->start, in lan966x_create_targets()
91 dev_err(&pdev->dev, "Unable to get registers: %s\n", in lan966x_create_targets()
92 iores[idx]->name); in lan966x_create_targets()
93 return -ENOMEM; in lan966x_create_targets()
[all …]
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pko.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
44 * - PKO indexes are no longer stored in the FAU. A large
48 * - The PKO <b>use_locking</b> parameter can now have a global
52 * - PKO 3 word commands are now supported. Use
60 #include <asm/octeon/cvmx-fpa.h>
61 #include <asm/octeon/cvmx-pow.h>
62 #include <asm/octeon/cvmx-cmd-queue.h>
63 #include <asm/octeon/cvmx-pko-defs.h>
[all …]
/openbmc/linux/drivers/scsi/lpfc/
H A Dlpfc_hw.h4 * Copyright (C) 2017-2023 Broadcom. All Rights Reserved. The term *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
[all …]
/openbmc/linux/Documentation/infiniband/
H A Dopa_vnic.rst2 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC)
5 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC) feature
6 supports Ethernet functionality over Omni-Path fabric by encapsulating
11 The patterns of exchanges of Omni-Path encapsulated Ethernet packets
12 involves one or more virtual Ethernet switches overlaid on the Omni-Path
13 fabric topology. A subset of HFI nodes on the Omni-Path fabric are
26 +-------------------+
30 +-------------------+
35 +-----------------------------+ +------------------------------+
37 | +---------+ +---------+ | | +---------+ +---------+ |
[all …]
/openbmc/u-boot/include/
H A Dns16550.h12 * reduced no of com ports to 2
15 * added support for port on 64-bit bus
31 #define CONFIG_SYS_NS16550_REG_SIZE (-1)
40 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
45 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
49 * struct ns16550_platdata - information about a NS16550 port
123 /* Ingenic JZ47xx specific UART-enable bit. */
139 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
147 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
150 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */
[all …]
/openbmc/linux/drivers/net/dsa/qca/
H A Dqca8k-8xxx.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
47 ret = bus->write(bus, phy_id, regnum, lo); in qca8k_mii_write_lo()
49 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_lo()
62 ret = bus->write(bus, phy_id, regnum, hi); in qca8k_mii_write_hi()
64 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_hi()
75 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_lo()
83 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_lo()
95 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_hi()
103 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_hi()
[all …]
/openbmc/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net_ctrl.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
17 /* 64-bit per app capabilities */
23 * THB-350, 32k needs to be reserved.
61 /* Hash type pre-pended when a RSS hash was computed */
80 /* Read/Write config words (0x0000 - 0x002c)
87 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
88 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes
92 * - define Error details in UPDATE
108 #define NFP_NET_CFG_CTRL_RXQINQ (0x1 << 13) /* Enable S-tag strip */
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_fw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2003-2014 QLogic Corporation
10 #include <linux/nvme-fc.h>
78 /* Bits 15-0 of word 0 */
80 /* Bits 15-0 of word 3 */
87 uint16_t prli_nvme_svc_param_word_0; /* Bits 15-0 of word 0 */
88 uint16_t prli_nvme_svc_param_word_3; /* Bits 15-0 of word 3 */
111 u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
112 u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
164 * BIT 1-15 =
[all …]
/openbmc/linux/drivers/thunderbolt/
H A Deeprom.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - eeprom access
16 * tb_eeprom_ctl_write() - write control word
20 return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1); in tb_eeprom_ctl_write()
24 * tb_eeprom_ctl_write() - read control word
28 return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1); in tb_eeprom_ctl_read()
37 * tb_eeprom_active - enable rom access
66 * tb_eeprom_transfer - transfer one bit
68 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->fl_do.
69 * If TB_EEPROM_OUT is passed, then ctl->fl_di will be written.
[all …]
/openbmc/u-boot/drivers/net/mscc_eswitch/
H A Docelot_switch.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
110 #define MAX_PORT (PORT3 - PORT0)
147 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; in mscc_miim_reset()
149 if (miim->phy_regs) { in mscc_miim_reset()
150 writel(0, miim->phy_regs + PHY_CFG); in mscc_miim_reset()
152 | PHY_CFG_ENA, miim->phy_regs + PHY_CFG); in mscc_miim_reset()
179 ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0, in ocelot_mdiobus_init()
190 phy_size[i] = res.end - res.start; in ocelot_mdiobus_init()
193 strcpy(bus->name, "miim-internal"); in ocelot_mdiobus_init()
196 bus->priv = &miim[INTERNAL]; in ocelot_mdiobus_init()
[all …]

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