| /openbmc/qemu/hw/misc/ |
| H A D | tz-ppc.c | 21 #include "hw/misc/tz-ppc.h"
22 #include "hw/qdev-properties.h"
26 bool level = s->irq_status && s->irq_enable; in tz_ppc_update_irq() local
28 trace_tz_ppc_update_irq(level); in tz_ppc_update_irq()
29 qemu_set_irq(s->irq, level); in tz_ppc_update_irq()
32 static void tz_ppc_cfg_nonsec(void *opaque, int n, int level) in tz_ppc_cfg_nonsec() argument
37 trace_tz_ppc_cfg_nonsec(n, level); in tz_ppc_cfg_nonsec()
38 s->cfg_nonsec[n] = level; in tz_ppc_cfg_nonsec()
41 static void tz_ppc_cfg_ap(void *opaque, int n, int level) in tz_ppc_cfg_ap() argument
46 trace_tz_ppc_cfg_ap(n, level); in tz_ppc_cfg_ap()
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| /openbmc/linux/Documentation/driver-api/serial/ |
| H A D | driver.rst | 2 Low Level Serial API
10 The reference implementation is contained within amba-pl011.c.
14 Low Level Serial Hardware Driver
15 --------------------------------
17 The low level serial hardware driver is responsible for supplying port
19 by uart_ops) to the core serial driver. The low level driver is also
20 responsible for handling interrupts for the port, and providing any
25 ---------------
28 the correct port structure (via uart_get_console()) and decoding command line
38 -------
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| /openbmc/linux/arch/arm/ |
| H A D | Kconfig.debug | 1 # SPDX-License-Identifier: GPL-2.0
44 once the kernel has booted up - it's a one time check.
107 1 - undefined instruction events
108 2 - system calls
109 4 - invalid data aborts
110 8 - SIGSEGV faults
111 16 - SIGBUS faults
115 bool "Kernel low-level debugging functions (read help!)"
128 prompt "Kernel low-level debugging port"
132 bool "Kernel low-level debugging messages via Alpine UART0"
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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dsi_dcs_backlight.c | 50 struct intel_panel *panel = &connector->panel; in dcs_get_backlight()
53 enum port port; in dcs_get_backlight() local
54 size_t len = panel->backlight.max > U8_MAX ? 2 : 1; in dcs_get_backlight()
56 for_each_dsi_port(port, panel->vbt.dsi.bl_ports) { in dcs_get_backlight()
57 dsi_device = intel_dsi->dsi_hosts[port]->device; in dcs_get_backlight()
66 static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32 level) in dcs_set_backlight() argument
68 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder)); in dcs_set_backlight()
69 struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; in dcs_set_backlight()
72 enum port port; in dcs_set_backlight() local
73 size_t len = panel->backlight.max > U8_MAX ? 2 : 1; in dcs_set_backlight()
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| H A D | intel_ddi.c | 94 int level; in intel_ddi_hdmi_level() local
96 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
97 if (level < 0) in intel_ddi_hdmi_level()
98 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
100 return level; in intel_ddi_hdmi_level()
114 * Starting with Haswell, DDI port buffers must be programmed with correct
121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
124 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers() local
127 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
128 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
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| /openbmc/linux/drivers/net/fddi/skfp/ |
| H A D | smtdef.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #define OEM_USER_DATA "SK-NET FDDI V2.0 Userdata"
67 void smt_reset_defaults(struct s_smc *smc, int level);
68 static void smt_init_mib(struct s_smc *smc, int level);
74 void smt_reset_defaults(struct s_smc *smc, int level) in smt_reset_defaults() argument
81 smt_init_mib(smc,level) ; in smt_reset_defaults()
83 smc->os.smc_version = SMC_VERSION ; in smt_reset_defaults()
86 smc->sm.last_tok_time[i] = smt_boot_time ; in smt_reset_defaults()
87 smt = &smc->s ; in smt_reset_defaults()
88 smt->attach_s = 0 ; in smt_reset_defaults()
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| /openbmc/linux/drivers/s390/scsi/ |
| H A D | zfcp_dbf.c | 1 // SPDX-License-Identifier: GPL-2.0
31 "log level for each debug feature area "
36 return sizeof(struct zfcp_dbf_pay) + offset - ZFCP_DBF_PAY_MAX_REC; in zfcp_dbf_plen()
43 struct zfcp_dbf_pay *pl = &dbf->pay_buf; in zfcp_dbf_pl_write()
46 spin_lock(&dbf->pay_lock); in zfcp_dbf_pl_write()
48 pl->fsf_req_id = req_id; in zfcp_dbf_pl_write()
49 memcpy(pl->area, area, ZFCP_DBF_TAG_LEN); in zfcp_dbf_pl_write()
53 (u16) (length - offset)); in zfcp_dbf_pl_write()
54 memcpy(pl->data, data + offset, rec_length); in zfcp_dbf_pl_write()
55 debug_event(dbf->pay, 1, pl, zfcp_dbf_plen(rec_length)); in zfcp_dbf_pl_write()
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| /openbmc/linux/drivers/scsi/libsas/ |
| H A D | sas_expander.c | 1 // SPDX-License-Identifier: GPL-2.0
29 /* ---------- SMP task management ---------- */
40 to_sas_internal(dev->port->ha->shost->transportt); in smp_execute_task_sg()
41 struct sas_ha_struct *ha = dev->port->ha; in smp_execute_task_sg()
43 pm_runtime_get_sync(ha->dev); in smp_execute_task_sg()
44 mutex_lock(&dev->ex_dev.cmd_mutex); in smp_execute_task_sg()
46 if (test_bit(SAS_DEV_GONE, &dev->state)) { in smp_execute_task_sg()
47 res = -ECOMM; in smp_execute_task_sg()
53 res = -ENOMEM; in smp_execute_task_sg()
56 task->dev = dev; in smp_execute_task_sg()
[all …]
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91_pio.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
9 * Parallel I/O Controller (PIO) - System peripherals registers.
59 u32 mder; /* 0x50 Multi-driver Enable Register */
60 u32 mddr; /* 0x54 Multi-driver Disable Register */
61 u32 mdsr; /* 0x58 Multi-driver Status Register */
63 u32 pudr; /* 0x60 Pull-up Disable Register */
64 u32 puer; /* 0x64 Pull-up Enable Register */
65 u32 pusr; /* 0x68 Pad Pull-up Status Register */
76 u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-stm32-usbphyc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
13 selects either OTG or HOST controller for the second PHY port. It also sets
19 |_ PHY port#1 _________________ HOST controller
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
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| /openbmc/linux/drivers/tty/serial/ |
| H A D | sc16is7xx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
44 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
47 * - only on 75x/76x
50 * - only on 75x/76x
53 * - only on 75x/76x
56 * - only on 75x/76x
62 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
84 /* IER register bits - write only if (EFR[4] == 1) */
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.txt | 31 implemented by the SoC. Each GPIO is assigned to a port, and a port may control
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
33 name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
37 implemented GPIOs within each port varies. GPIO registers within a controller
38 are grouped and laid out according to the port they affect.
40 The mapping from port name to the GPIO controller that implements that port, and
41 the mapping from port name to register offset within a controller, are both
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
52 both the overall controller HW module and the sets-of-ports as "controllers".
[all …]
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| /openbmc/openbmc/poky/bitbake/bin/ |
| H A D | bitbake-hashserv | 5 # SPDX-License-Identifier: GPL-2.0-only
33 unix://PATH - Bind to unix domain socket at PATH
34 ws://ADDRESS:PORT - Bind to websocket on ADDRESS:PORT
35 ADDRESS:PORT - Bind to raw TCP socket on ADDRESS:PORT
37 To bind to all addresses, leave the ADDRESS empty, e.g. "--bind :8686" or
38 "--bind ws://:8686". To bind to a specific IPv6 address, enclose the address in
39 "[]", e.g. "--bind [::1]:8686" or "--bind ws://[::1]:8686"
43 you want to use authentication, it is recommended that you use "--anon-perms
44 @read" to only give anonymous users read access, or "--anon-perms @none" to
45 give un-authenticated users no access at all.
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|
| H A D | bitbake-prserv | 5 # SPDX-License-Identifier: GPL-2.0-only
27 raise ValueError("Invalid log level: %s" % loglevel)
28 FORMAT = "%(asctime)-15s %(message)s"
29 logging.basicConfig(level=numeric_level, filename=logfile, format=FORMAT)
37 "-f",
38 "--file",
43 "-l",
44 "--log",
49 "--loglevel",
51 help="logging level, i.e. CRITICAL, ERROR, WARNING, INFO, DEBUG",
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| /openbmc/linux/Documentation/netlabel/ |
| H A D | draft-ietf-cipso-ipsecurity-01.txt | 12 This Internet Draft provides the high level specification for a Commercial
27 Please check the I-D abstract listing contained in each Internet Draft
46 mandatory access controls and multi-level security. These systems are
88 once in a datagram. All multi-octet fields in the option are defined to be
91 +----------+----------+------//------+-----------//---------+
93 +----------+----------+------//------+-----------//---------+
124 corresponding ASCII representations. Non-related groups of systems may
138 number 1 to represent that same security level. The DOI identifier is used
148 actual security information to be passed. All multi-octet fields in a tag
171 +----------+----------+--------//--------+
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
42 implemented by the SoC. Each GPIO is assigned to a port, and a port may
44 alphabetical port name and an integer GPIO name within the port. For
48 of implemented GPIOs within each port varies. GPIO registers within a
49 controller are grouped and laid out according to the port they affect.
[all …]
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| /openbmc/linux/Documentation/arch/m68k/ |
| H A D | buddha-driver.rst | 8 ------------------------------------------------------------------------
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
41 $0-$7e Autokonfig-space, see Z-II docs.
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| /openbmc/phosphor-logging/phosphor-rsyslog-config/ |
| H A D | server-conf.cpp | 1 #include "server-conf.hpp"
6 #include <phosphor-logging/elog.hpp>
9 #if __has_include("../../usr/include/phosphor-logging/elog-errors.hpp")
10 #include "../../usr/include/phosphor-logging/elog-errors.hpp"
12 #include <phosphor-logging/elog-errors.hpp>
53 //"*.* @@<address>:<port>" or in parseConfig()
54 //"*.* @@[<ipv6-address>:<port>" in parseConfig()
91 line.substr(posColonLeft + 1, posColonRight - posColonLeft - 1); in parseConfig()
102 serverAddress = line.substr(start, pos - start); in parseConfig()
117 log<level::ERR>("Invalid config", entry("ERR=%s", ex.what())); in parseConfig()
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| /openbmc/linux/drivers/parisc/ |
| H A D | eisa.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * eisa.c - provide support for EISA adapters in PA-RISC machines
10 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15 * -----
17 * set an edge trigger level. This may be done on the palo command line
38 #include <asm/parisc-device.h>
67 /* Port ops */
69 static inline unsigned long eisa_permute(unsigned short port) in eisa_permute() argument
71 if (port & 0x300) { in eisa_permute()
72 return 0xfc000000 | ((port & 0xfc00) >> 6) in eisa_permute()
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| /openbmc/linux/arch/arm64/boot/dts/synaptics/ |
| H A D | berlin4ct.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "arm,psci-1.0", "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a53";
33 enable-method = "psci";
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| /openbmc/linux/Documentation/scsi/ |
| H A D | advansys.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
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| /openbmc/linux/drivers/xen/events/ |
| H A D | events_2l.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xen event channels (2-level ABI)
19 #include <xen/xen-ops.h>
62 static void evtchn_2l_clear_pending(evtchn_port_t port) in evtchn_2l_clear_pending() argument
65 sync_clear_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_clear_pending()
68 static void evtchn_2l_set_pending(evtchn_port_t port) in evtchn_2l_set_pending() argument
71 sync_set_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_set_pending()
74 static bool evtchn_2l_is_pending(evtchn_port_t port) in evtchn_2l_is_pending() argument
77 return sync_test_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_is_pending()
80 static void evtchn_2l_mask(evtchn_port_t port) in evtchn_2l_mask() argument
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| /openbmc/linux/Documentation/admin-guide/ |
| H A D | thunderbolt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 some differences at the register level among other things. Connection
18 software connection manager in Linux also advertises security level
21 the software connection manager only supports ``user`` security level and
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
44 security levels available. Intel Titan Ridge added one more security level
51 treated as another security level (nopcie).
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-dwapb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 #include "gpiolib-acpi.h"
47 #define DWAPB_DRIVER_NAME "gpio-dwapb"
83 /* Store GPIO context across system-wide suspend/resume transitions */
112 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
144 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2) in gpio_reg_convert()
152 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_read()
153 void __iomem *reg_base = gpio->regs; in dwapb_read()
155 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); in dwapb_read()
161 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_write()
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | marvell-orion-net.txt | 9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
11 the multiple levels is that the port registers are interleaved within a single
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
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|