| /openbmc/linux/include/media/i2c/ |
| H A D | tvp7002.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
19 * struct tvp7002_config - Platform dependent data
20 *@clk_polarity: Clock polarity
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
23 *@hs_polarity: HSYNC polarity
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
25 *@vs_polarity: VSYNC Polarity
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| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | tvp7002.txt | 7 - compatible : Must be "ti,tvp7002"
10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
16 - pclk-sample: Clock polarity of the bus. Default value when this property is
19 - sync-on-green-active: Active state of Sync-on-green signal property of the
21 0 = Normal Operation (Active Low, Default)
24 - field-even-active: Active-high Field ID output polarity control of the bus.
27 0 = Normal Operation (Active Low, Default)
28 1 = FID output polarity inverted
31 video-interfaces.txt.
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | m88ds3103.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
52 * @ts_clk_pol: TS clk polarity. 1-active at falling edge; 0-active at rising
56 * @agc_inv: AGC polarity.
59 * @lnb_hv_pol: LNB H/V pin polarity. 0: pin high set to VOLTAGE_18, pin low to
60 * set VOLTAGE_13. 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18.
61 * @lnb_en_pol: LNB enable pin polarity. 0: pin high to disable, pin low to
62 * enable. 1: pin high to enable, pin low to disable.
88 * struct m88ds3103_config - m88ds3102 configuration
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| /openbmc/linux/drivers/media/platform/ti/omap3isp/ |
| H A D | omap3isp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
31 * @clk_pol: Pixel clock polarity
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
33 * @hs_pol: Horizontal synchronization polarity
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| /openbmc/skeleton/libopenbmc_intf/ |
| H A D | gpio_configs.c | 9 * http://www.apache.org/licenses/LICENSE-2.0
29 * Loads the GPIO information into the gpios->power_gpio structure
32 * @param gpios - the structure where GpioConfigs.power_gpio will
34 * @param gpio_configs - cJSON pointer to the GPIO JSON
44 /* PGOOD - required */ in read_power_gpios()
49 gpios->power_gpio.power_good_in.name = g_strdup(pgood->valuestring); in read_power_gpios()
52 gpios->power_gpio.power_good_in.name); in read_power_gpios()
54 /* Latch out - optional */ in read_power_gpios()
59 gpios->power_gpio.latch_out.name = g_strdup(latch->valuestring); in read_power_gpios()
61 gpios->power_gpio.latch_out.name); in read_power_gpios()
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| /openbmc/linux/Documentation/devicetree/bindings/display/panel/ |
| H A D | panel-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
24 width-mm:
29 height-mm:
43 non-descriptive information. For instance an LCD panel in a system that
55 panel-timing:
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio.txt | 5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
39 such as if the consumer desire the line to be active low (inverted) or open
44 recommended to use the two-cell approach.
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | ds1621.rst | 47 - Christian W. Zuckschwerdt <zany@triq.net>
48 - valuable contributions by Jan M. Sendler <sendler@sendler.de>
49 - ported to 2.6 by Aurelien Jarno <aurelien@aurel32.net>
53 ------------------
55 * polarity int
56 Output's polarity:
58 * 0 = active high,
59 * 1 = active low
62 -----------
65 both high and low temperature limits which can be user defined (i.e.
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| /openbmc/linux/Documentation/firmware-guide/acpi/ |
| H A D | gpio-properties.rst | 1 .. SPDX-License-Identifier: GPL-2.0
31 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
34 Package () { "reset-gpios", Package () { ^BTH, 1, 1, 0 } },
35 Package () { "shutdown-gpios", Package () { ^BTH, 0, 0, 0 } },
55 active low or high, the "active_low" argument can be used here. Setting
56 it to 1 marks the GPIO as active low.
61 In our Bluetooth example the "reset-gpios" refers to the second GpioIo()
68 and polarity settings. The table below shows the expectations:
70 +-------------+-------------+-----------------------------------------------+
71 | Pull Bias | Polarity | Requested... |
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| /openbmc/linux/include/dt-bindings/sound/ |
| H A D | cs35l45.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
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| /openbmc/linux/Documentation/devicetree/bindings/regulator/ |
| H A D | richtek,rtmv20-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
43 richtek,ld-pulse-width-us:
50 richtek,fsin1-delay-us:
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| H A D | gpio-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/gpio-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
18 - $ref: regulator.yaml#
22 const: regulator-gpio
24 regulator-name: true
26 enable-gpios:
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | fsl,imx8mp-dwc3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Li Jun <jun.li@nxp.com>
15 const: fsl,imx8mp-dwc3
19 - description: Address and length of the register set for HSIO Block Control
20 - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
22 "#address-cells":
25 "#size-cells":
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| H A D | ci-hdrc-usb2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
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| /openbmc/linux/Documentation/fb/ |
| H A D | pxafb.rst | 10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
53 active | passive => LCCR0_PAS
55 Active (TFT) or Passive (STN) display
67 Horizontal and vertical sync. 0 => active low, 1 => active
74 outputen:POLARITY
76 Output Enable Polarity. 0 => active low, 1 => active high
78 pixclockpol:POLARITY
80 pixel clock polarity
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| /openbmc/u-boot/drivers/video/ |
| H A D | am335x-fb.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
4 * B&R Industrial Automation GmbH - http://www.br-automation.com
29 * 0 = DE is low-active
30 * 1 = DE is high-active
33 * 0 = pix-clk is high-active
34 * 1 = pic-clk is low-active
37 * 0 = HSYNC is active high
38 * 1 = HSYNC is avtive low
41 * 0 = VSYNC is active high
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | gpio.txt | 5 -----------------
8 properties, each containing a 'gpio-list':
10 gpio-list ::= <single-gpio> [gpio-list]
11 single-gpio ::= <gpio-phandle> <gpio-specifier>
12 gpio-phandle : phandle to gpio controller node
13 gpio-specifier : Array of #gpio-cells specifying specific gpio
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
31 and bit-banged data signals:
34 gpio-controller
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| H A D | nvidia,tegra20-gpio.txt | 4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
19 4 = active high level-sensitive.
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| /openbmc/linux/Documentation/devicetree/bindings/display/exynos/ |
| H A D | exynos_dp.txt | 5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
17 -compatible:
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| /openbmc/linux/Documentation/devicetree/bindings/serial/ |
| H A D | nxp,sc16is7xx.txt | 1 * NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
5 - compatible: Should be one of the following:
6 - "nxp,sc16is740" for NXP SC16IS740,
7 - "nxp,sc16is741" for NXP SC16IS741,
8 - "nxp,sc16is750" for NXP SC16IS750,
9 - "nxp,sc16is752" for NXP SC16IS752,
10 - "nxp,sc16is760" for NXP SC16IS760,
11 - "nxp,sc16is762" for NXP SC16IS762.
12 - reg: I2C address of the SC16IS7xx device.
13 - interrupts: Should contain the UART interrupt
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| H A D | rs485.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
18 description: prop-encoded-array <a b>
19 $ref: /schemas/types.yaml#/definitions/uint32-array
21 - description: Delay between rts signal and beginning of data sent in
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | pwm.rst | 15 ----------------
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
73 PWM arguments are usually platform-specific and allows the PWM user to only
75 period). struct pwm_args contains 2 fields (period and polarity) and should
84 -----------------------------------
93 The number of PWM channels this chip supports (read-only).
96 Exports a PWM channel for use with sysfs (write-only).
99 Unexports a PWM channel from sysfs (write-only).
101 The PWM channels are numbered using a per-chip index from 0 to npwm-1.
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| /openbmc/linux/sound/soc/ti/ |
| H A D | davinci-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
31 #include "edma-pcm.h"
32 #include "davinci-i2s.h"
34 #define DRV_NAME "davinci-i2s"
39 * - This driver supports the "Audio Serial Port" (ASP),
42 * - But it labels it a "Multi-channel Buffered Serial Port"
44 * backward-compatible, possibly explaining that confusion.
46 * - OMAP chips have a controller called McBSP, which is
49 * - Newer DaVinci chips have a controller called McASP,
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | pxa3xx-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
69 #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
71 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
90 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
96 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
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| /openbmc/linux/drivers/usb/chipidea/ |
| H A D | ci_hdrc_imx.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
15 /* true if over-current polarity is active low */
18 /* true if dt specifies polarity */
21 unsigned int pwr_pol:1; /* power polarity */
|