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Searched +full:pmic +full:- +full:arbiter (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/spmi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 SPMI (System Power Management Interface) is a two-wire
10 and Power Management Integrated Circuits (PMIC).
20 built-in SPMI PMIC Arbiter interface on Hisilicon 3670
24 tristate "Qualcomm MSM SPMI Controller (PMIC Arbiter)"
31 built-in SPMI PMIC Arbiter interface on Qualcomm MSM family
38 tristate "Mediatek SPMI Controller (PMIC Arbiter)"
42 built-in SPMI PMIC Arbiter interface on Mediatek family
H A Dspmi-pmic-arb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.
20 /* PMIC Arbiter configuration registers */
33 /* PMIC Arbiter channel registers offsets */
50 #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
89 * PMIC arbiter version 5 uses different register offsets for read/write vs
97 /* Maximum number of support PMIC peripherals */
129 * struct spmi_pmic_arb - SPMI PMIC Arbiter object
134 * @cnfg: address of the PMIC Arbiter configuration registers.
137 * @irq: PMIC ARB interrupt.
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/openbmc/linux/Documentation/devicetree/bindings/spmi/
H A Dqcom,spmi-pmic-arb.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SPMI Controller (PMIC Arbiter)
10 - Stephen Boyd <sboyd@kernel.org>
13 The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
14 controller with wrapping arbitration logic to allow for multiple on-chip
17 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
21 - $ref: spmi.yaml
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/openbmc/u-boot/doc/device-tree-bindings/spmi/
H A Dspmi-msm.txt1 Qualcomm SPMI arbiter/bus driver
6 - compatible: "qcom,spmi-pmic-arb"
7 - reg: Register block adresses and sizes for various parts of device:
8 1) PMIC arbiter channel mapping base (PMIC_ARB_REG_CHNLn)
13 - #address-cells: 0x1 - childs slave ID address
14 - #size-cells: 0x1
16 All PMICs should be placed as a child nodes of bus arbiter.
22 compatible = "qcom,spmi-pmic-arb";
24 #address-cells = <0x1>;
25 #size-cells = <0x1>;
H A Dspmi-sandbox.txt1 Sandbox SPMI emulated arbiter.
3 This is bus driver for Sandbox. It includes part of emulated pm8916 pmic.
6 - compatible: "sandbox,spmi"
7 - #address-cells: 0x1 - childs slave ID address
8 - #size-cells: 0x1
14 #address-cells = <0x1>;
15 #size-cells = <0x1>;
17 compatible = "qcom,spmi-pmic";
19 #address-cells = <0x1>;
20 #size-cells = <0x1>;
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/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ssbi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Single-wire Serial Bus Interface (SSBI)
10 Some Qualcomm MSM devices contain a point-to-point serial bus used to
15 - Andy Gross <agross@kernel.org>
16 - Bjorn Andersson <andersson@kernel.org>
25 qcom,controller-type:
31 - ssbi
32 - ssbi2
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/openbmc/linux/drivers/mfd/
H A Dssbi.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
8 * - Largely rewritten from original to not be an i2c driver.
46 /* SSBI PMIC Arbiter command registers */
77 return readl(ssbi->base + reg); in ssbi_readl()
82 writel(val, ssbi->base + reg); in ssbi_writel()
88 * case, is when using the arbiter and both other CPUs have just
99 while (timeout--) { in ssbi_wait_mask()
106 return -ETIMEDOUT; in ssbi_wait_mask()
115 if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) { in ssbi_read_bytes()
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/openbmc/u-boot/drivers/spmi/
H A Dspmi-msm.c1 // SPDX-License-Identifier: BSD-3-Clause
19 /* PMIC Arbiter configuration registers */
63 return -EIO; in msm_spmi_write()
65 return -EIO; in msm_spmi_write()
67 channel = priv->channel_map[usid][pid]; in msm_spmi_write()
70 writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) + in msm_spmi_write()
74 writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA); in msm_spmi_write()
84 writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0); in msm_spmi_write()
89 reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) + in msm_spmi_write()
95 return -EIO; in msm_spmi_write()
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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
8 #include <dt-bindings/mfd/qcom-rpm.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
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H A Dqcom-mdm9615.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
13 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
15 #include <dt-bindings/mfd/qcom-rpm.h>
16 #include <dt-bindings/soc/qcom,gsbi.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
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H A Dqcom-msm8660.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
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H A Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
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H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
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/openbmc/linux/drivers/iio/adc/
H A Dqcom-pm8xxx-xoadc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm PM8xxx PMIC XOADC driver
7 * specific-purpose and general purpose ADC converters and channels.
13 #include <linux/iio/adc/qcom-vadc-common.h>
27 * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC:
28 * drivers/misc/pmic8058-xoadc.c
29 * drivers/hwmon/pm8xxx-adc.c
155 * struct xoadc_channel - encodes channel properties and defaults
162 * @prescale: the channels have hard-coded prescale ratios defined
185 * struct xoadc_variant - encodes the XOADC variant characteristics
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/openbmc/linux/drivers/soc/mediatek/
H A Dmtk-pmic-wrap.c1 // SPDX-License-Identifier: GPL-2.0-only
1337 * pwrap operations are highly associated with the PMIC types,
1346 * struct pwrap_slv_type - PMIC device wrapper definitions
1348 * @type: PMIC Type (model)
1350 * @comp_type: Companion PMIC Type (model)
1395 return readl(wrp->base + wrp->master->regs[reg]); in pwrap_readl()
1400 writel(val, wrp->base + wrp->master->regs[reg]); in pwrap_writel()
1408 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) in pwrap_get_fsm_state()
1426 * failed because pmic wrap could not got the FSM_VLDCLR
1464 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) in pwrap_read16()
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