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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-tcon-ch0-clk.yaml64 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
73 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
H A Dallwinner,sun4i-a10-display-clk.yaml53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun50i_h6.h21 u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
39 u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */
40 u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */
65 u32 pll7_bias; /* 0x330 pll7 (gpu) bias */
H A Dclock_sun8i_a83t.h29 u32 pll7_cfg; /* 0x38 pll7 gpu control */
102 u32 pll8_bias_cfg; /* 0x23c PLL7 Bias config */
H A Dclock_sun6i.h26 u32 pll7_cfg; /* 0x30 pll7 control */
136 u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
150 u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
H A Dclock_sun4i.h26 u32 pll7_cfg; /* 0x30 pll7 control */
/openbmc/linux/drivers/clk/
H A Dclk-milbeaut.c26 #define M10V_PLL7 "pll7"
27 #define M10V_PLL7DIV2 "pll7-2"
28 #define M10V_PLL7DIV5 "pll7-5"
/openbmc/qemu/hw/misc/
H A Dallwinner-a10-ccm.c43 REG_PLL7_CFG = 0x0030, /* PLL7 Control */
/openbmc/linux/drivers/clk/imx/
H A Dclk-vf610.c83 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
225 …clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll7", "pll7_bypass_src", PLL7_CTRL,… in vf610_clocks_init()
H A Dclk-imx6sll.c29 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
129 …hws[IMX6SLL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0… in imx6sll_clocks_init()
H A Dclk-imx6sl.c70 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
223 hws[IMX6SL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); in imx6sl_clocks_init()
H A Dclk-imx6ul.c28 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
169 hws[IMX6UL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); in imx6ul_clocks_init()
H A Dclk-imx6sx.c83 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
166 hws[IMX6SX_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); in imx6sx_clocks_init()
H A Dclk-imx6q.c91 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
488 hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); in imx6q_clocks_init()
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_async_ids_map_extended.h272 { .fc_id = 246, .cpu_id = 119, .valid = 1, .name = "PLL7" },