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/openbmc/linux/drivers/clk/sunxi/
H A Dclk-a10-pll2.c16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup()
73 /* Setup the gate part of the PLL2 */ in sun4i_pll2_setup()
82 /* Setup the multiplier part of the PLL2 */ in sun4i_pll2_setup()
95 base_clk = clk_register_composite(NULL, "pll2-base", in sun4i_pll2_setup()
109 * PLL2-1x in sun4i_pll2_setup()
130 * PLL2-2x in sun4i_pll2_setup()
133 * a fixed divider from the PLL2 base clock. in sun4i_pll2_setup()
143 /* PLL2-4x */ in sun4i_pll2_setup()
152 /* PLL2-8x */ in sun4i_pll2_setup()
[all …]
/openbmc/linux/include/linux/iio/frequency/
H A Dad9523.h126 * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
127 * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
128 * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
129 * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
130 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
133 * @rpole2: PLL2 loop filter Rpole resistor value.
134 * @rzero: PLL2 loop filter Rzero resistor value.
135 * @cpole1: PLL2 loop filter Cpole capacitor value.
136 * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
172 /* PLL2 Setting */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-mod1-clk.yaml44 #include <dt-bindings/clock/sun4i-a10-pll2.h>
50 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
51 <&pll2 SUN4I_A10_PLL2_4X>,
52 <&pll2 SUN4I_A10_PLL2_2X>,
53 <&pll2 SUN4I_A10_PLL2_1X>;
H A Dstarfive,jh7110-syscrg.yaml32 - description: PLL2
46 - description: PLL2
H A Drenesas,cpg-clocks.yaml76 - const: pll2
202 - const: pll2
/openbmc/linux/sound/soc/codecs/
H A Dak4642.c114 #define PLL2 (1 << 6) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
345 pll = PLL2; in ak4642_dai_set_sysclk()
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
H A Dadav80x.c207 SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0),
223 clk = "PLL2"; in adav80x_dapm_sysclk_check()
270 { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check },
273 { "PLL2", NULL, "OSC", adav80x_dapm_pll_check },
610 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2"); in adav80x_set_sysclk()
612 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2"); in adav80x_set_sysclk()
810 snd_soc_dapm_force_enable_pin(dapm, "PLL2"); in adav80x_probe()
/openbmc/linux/drivers/mfd/
H A Dsm501.c116 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
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/openbmc/linux/drivers/clk/mmp/
H A Dclk-of-mmp2.c107 {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
112 …{MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000…
127 {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
131 {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
300 static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
311 static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
318 … * const mmp2_gpu_gc_parent_names[] = {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"};
320 static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2", "pll2_2", "usb_pll"};
323 static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"};
/openbmc/linux/arch/arm/mach-ep93xx/
H A Dclock.c41 "pll2"
581 /* Determine the bootloader configured pll2 rate */ in ep93xx_clock_init()
590 hw = clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate); in ep93xx_clock_init()
591 clk_hw_register_clkdev(hw, NULL, "pll2"); in ep93xx_clock_init()
593 /* Initialize the pll2 derived clocks */ in ep93xx_clock_init()
595 * These four bits set the divide ratio between the PLL2 in ep93xx_clock_init()
616 hw = clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_usb_div); in ep93xx_clock_init()
640 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", in ep93xx_clock_init()
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/openbmc/linux/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
293 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
300 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
316 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
323 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/openbmc/u-boot/drivers/video/tegra124/
H A Dsor.c486 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
507 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
518 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
524 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
563 DUMP_REG(PLL2); in dump_sor_reg()
700 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
714 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
724 if (tegra_dc_sor_poll_register(sor, PLL2, in tegra_dc_sor_enable_dp()
732 tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | in tegra_dc_sor_enable_dp()
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dums512.dtsi291 pll2: clock-controller@0 { label
686 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
703 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
720 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
737 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
754 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
771 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
788 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
805 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun9i.c29 /* Set up PLL1 (cluster 0) and PLL2 (cluster 1) */ in clock_init_safe()
118 /* Switch cluster 1 to 24MHz clock while changing PLL2 */ in clock_set_pll2()
128 /* Switch cluster 1 back to PLL2 */ in clock_set_pll2()
/openbmc/linux/drivers/media/i2c/
H A Dsaa711x_regs.h181 /* second PLL (PLL2) and Pulsegenerator Programming */
535 /* second PLL (PLL2) and Pulsegenerator Programming */
541 "Nominal PLL2 DTO"},
543 "PLL2 Increment"},
545 "PLL2 Status"},
558 "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h19 u32 pll2_cfg; /* 0x08 pll2 audio control */
96 u32 pll2_bias_cfg; /* 0x224 PLL2 audio Bias config */
110 u32 pll2_pattern_cfg0; /* 0x284 PLL2 Pattern register 0 */
115 u32 pll2_pattern_cfg1; /* 0x2a4 PLL2 Pattern register 1 */
H A Dclock_sun50i_h6.h33 u32 pll2_cfg; /* 0x078 pll2 (audio) control */
54 u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */
55 u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */
77 u32 pll2_bias; /* 0x378 pll2 (audio) bias */
/openbmc/linux/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); in mx28_clocks_init()
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi196 * that is parent of TIMCLK, PLL1 and PLL2
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
242 pll2: pll2@0 { label
253 clocks = <&pll2>;
268 clocks = <&pll2>;
276 clocks = <&pll2>;
/openbmc/linux/drivers/clk/renesas/
H A Dr8a779f0-cpg-mssr.c62 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
191 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dlowlevel_init.S145 /* Program the PLL2 Divisor Value */
150 /* Program the PLL2 Divisor Value */
155 /* PLL2 DIV2 MMR */
178 /* PLL2 DIV1 MMR */
665 /* PLL2-SYSTEM PLL MMRs */
/openbmc/qemu/hw/misc/
H A Dallwinner-a10-ccm.c35 REG_PLL2_CFG = 0x0008, /* PLL2 Control */
36 REG_PLL2_TUN = 0x000C, /* PLL2 Tuning */
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmediatek,mt8188-afe.yaml49 - description: audio pll2 clock
66 - description: audio pll2 divide 4

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