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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll1-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
47 compatible = "allwinner,sun4i-a10-pll1-clk";
56 compatible = "allwinner,sun6i-a31-pll1-clk";
59 clock-output-names = "pll1";
65 compatible = "allwinner,sun8i-a23-pll1-clk";
68 clock-output-names = "pll1";
H A Dqoriq-clock.txt168 pll1: pll1@820 {
173 clock-output-names = "pll1", "pll1-div2";
180 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
181 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
189 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
190 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
H A Dmicrochip,mpfs-ccc.yaml25 - description: PLL1's control registers
37 - description: PLL1's refclk0
38 - description: PLL1's refclk1
H A Dsilabs,si5351.txt82 /* connect xtal input as source of pll0 and pll1 */
105 * - pll1 as clock source of multisynth1
107 * - multisynth1 can change pll1
H A Dstarfive,jh7110-syscrg.yaml31 - description: PLL1
45 - description: PLL1
/openbmc/linux/include/linux/iio/frequency/
H A Dad9523.h117 * @refa_r_div: PLL1 10-bit REFA R divider.
118 * @refb_r_div: PLL1 10-bit REFB R divider.
119 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
120 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
122 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
124 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
160 /* PLL1 Setting */
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
/openbmc/linux/drivers/clk/renesas/
H A Dclk-sh73a0.c48 { "m3", "pll1", CPG_FRQCRA, 12 },
49 { "b", "pll1", CPG_FRQCRA, 8 },
50 { "m1", "pll1", CPG_FRQCRA, 4 },
51 { "m2", "pll1", CPG_FRQCRA, 0 },
52 { "zx", "pll1", CPG_FRQCRB, 12 },
53 { "hp", "pll1", CPG_FRQCRB, 4 },
112 /* handle CFG bit for PLL1 and PLL2 */ in sh73a0_cpg_register_clock()
H A Dr8a77470-cpg-mssr.c45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
173 * MD EXTAL PLL0 PLL1 PLL3
182 * *2 : Table 7.4 indicates VCO output (PLL1 = VCO)
188 /* EXTAL div PLL1 mult x2 PLL3 mult */
H A Dr8a7745-cpg-mssr.c45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
190 * MD EXTAL PLL0 PLL1 PLL3
199 * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
205 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
/openbmc/u-boot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg32 ; This section allows setting up the PLL1. Usually this will
57 ; This section can be used to configure the PLL1 and the EMIF3a registers
155 ; This section allows setting up the PLL1. Usually this will
165 ; This section can be used to configure the PLL1 and the EMIF3a registers
182 ; This section can be used to configure the PLL1 and the EMIF3a registers
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun9i.c29 /* Set up PLL1 (cluster 0) and PLL2 (cluster 1) */ in clock_init_safe()
36 /* Set up dividers for AXI0 and APB0 on cluster 0: PLL1 / 2 = 204MHz */ in clock_init_safe()
91 /* Switch cluster 0 to 24MHz clock while changing PLL1 */ in clock_set_pll1()
107 /* Switch cluster 0 back to PLL1 */ in clock_set_pll1()
H A Dclock_sun50i_h6.c62 /* Switch to 24MHz clock while changing PLL1 */ in clock_set_pll1()
73 /* Switch CPU to PLL1 */ in clock_set_pll1()
H A Dclock_sun6i.c125 /* Switch to 24MHz clock while changing PLL1 */ in clock_set_pll1()
132 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) in clock_set_pll1()
133 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m in clock_set_pll1()
140 /* Switch CPU to PLL1 */ in clock_set_pll1()
/openbmc/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,clkgen-pll.txt15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
/openbmc/linux/drivers/clk/
H A Dclk-k210.c300 * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
302 * rate divided by 2. Set PLL1 to 390 MHz so that the third SRAM bank has the
576 /* PLL0 and PLL1 only have IN0 as parent */ in k210_register_plls()
582 ret = k210_register_pll(np, ksc, K210_PLL1, "pll1", 1, &k210_pll_ops); in k210_register_plls()
584 pr_err("%pOFP: register PLL1 failed\n", np); in k210_register_plls()
588 /* PLL2 has IN0, PLL0 and PLL1 as parents */ in k210_register_plls()
998 * Enable PLL1 to be able to use the AI SRAM.
1002 struct k210_pll pll1; in k210_clk_early_init() local
1007 /* Startup PLL1 to enable the aisram bank for general memory use */ in k210_clk_early_init()
1008 k210_init_pll(regs, K210_PLL1, &pll1); in k210_clk_early_init()
[all …]
/openbmc/linux/Documentation/arch/arm/sunxi/
H A Dclocks.rst20 PLL1
31 PLL1 |
/openbmc/linux/arch/arm/mach-ep93xx/
H A Dclock.c40 "pll1",
555 /* Determine the bootloader configured pll1 rate */ in ep93xx_clock_init()
562 hw = clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate); in ep93xx_clock_init()
563 clk_hw_register_clkdev(hw, NULL, "pll1"); in ep93xx_clock_init()
565 /* Initialize the pll1 derived clocks */ in ep93xx_clock_init()
570 hw = clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div); in ep93xx_clock_init()
572 hw = clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div); in ep93xx_clock_init()
640 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", in ep93xx_clock_init()
/openbmc/linux/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
292 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
299 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
315 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
41 /* m is always zero for pll1 */ in sun4i_get_pll1_factors()
75 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
76 * PLL1 rate is calculated as follows
151 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
152 * PLL1 rate is calculated as follows
165 /* m is always zero for pll1 */ in sun8i_a23_get_pll1_factors()
575 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
582 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
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/openbmc/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
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/openbmc/linux/sound/soc/codecs/
H A Dadav80x.c206 SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0),
220 clk = "PLL1"; in adav80x_dapm_sysclk_check()
269 { "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check },
272 { "PLL1", NULL, "OSC", adav80x_dapm_pll_check },
605 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL1"); in adav80x_set_sysclk()
607 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL1"); in adav80x_set_sysclk()
809 snd_soc_dapm_force_enable_pin(dapm, "PLL1"); in adav80x_probe()
/openbmc/qemu/hw/misc/
H A Dallwinner-a10-ccm.c33 REG_PLL1_CFG = 0x0000, /* PLL1 Control */
34 REG_PLL1_TUN = 0x0004, /* PLL1 Tuning */
44 REG_PLL1_TUN2 = 0x0038, /* PLL1 Tuning2 */
/openbmc/linux/drivers/gpu/drm/tegra/
H A Dhdmi.c43 u32 pll1; member
141 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
156 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
174 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
202 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
219 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
237 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
256 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
275 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
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