| /openbmc/linux/drivers/media/i2c/ |
| H A D | ccs-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
25 /* CCS PLL flags */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
42 * @pll_multiplier: PLL multiplier
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| H A D | aptina-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aptina Sensor PLL Configuration
13 #include "aptina-pll.h"
17 struct aptina_pll *pll) in aptina_pll_calculate() argument
26 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
27 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
31 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
32 return -EINVAL; in aptina_pll_calculate()
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5 multiple phase locked loops (PLL) to create a variety of frequencies
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
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| H A D | silabs,si5351.txt | 1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
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| H A D | silabs,si5341.txt | 2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
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| H A D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
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| H A D | starfive,jh7110-pll.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PLL Clock Generator
10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
11 Each PLL works in integer mode or fraction mode, with configuration
13 SYS-SYSCON node.
14 The formula for calculating frequency is
18 - Xingyu Wu <xingyu.wu@starfivetech.com>
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| /openbmc/linux/drivers/staging/sm750fb/ |
| H A D | ddk750_chip.c | 1 // SPDX-License-Identifier: GPL-2.0
52 * This function set up the main chip clock.
54 * Input: Frequency to be set.
56 static void set_chip_clock(unsigned int frequency) in set_chip_clock() argument
58 struct pll_value pll; in set_chip_clock() local
60 /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ in set_chip_clock()
64 if (frequency) { in set_chip_clock()
66 * Set up PLL structure to hold the value to be set in clocks. in set_chip_clock()
68 pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in set_chip_clock()
69 pll.clock_type = MXCLK_PLL; in set_chip_clock()
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| /openbmc/linux/drivers/clk/zynq/ |
| H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
17 * @pll_ctrl: PLL control register
18 * @pll_status: PLL status register
20 * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
45 * zynq_pll_round_rate() - Round a clock frequency
46 * @hw: Handle between common and hardware-specific interfaces
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | st,stm32h7-rcc.txt | 1 STMicroelectronics STM32H7 Reset and Clock Controller
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32h743-rcc"
13 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
18 - #clock-cells : from common clock binding; shall be set to 1
20 - clocks: External oscillator clock phandle
21 - high speed external clock signal (HSE)
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| H A D | st,stm32mp1.txt | 1 STMicroelectronics STM32MP1 clock tree initialization
4 The STM32MP clock tree initialization is based on device tree information
7 -------------------------------
8 RCC CLOCK = st,stm32mp1-rcc-clk
9 -------------------------------
11 The RCC IP is both a reset and a clock controller but this documentation only
12 describes the fields added for clock tree initialization which are not present
15 Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
20 - compatible: Should be "st,stm32mp1-rcc-clk"
22 - st,clksrc : The clock source in this order
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| /openbmc/linux/drivers/clk/zynqmp/ |
| H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
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| /openbmc/u-boot/drivers/clk/sifive/ |
| H A D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
19 * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
21 * integrates this PLL; thus the register structure and programming
24 * The bulk of this code is primarily useful for clock configurations
25 * that must operate at arbitrary rates, as opposed to clock configurations
27 * pre-determined set of performance points.
30 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
31 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
39 #include "analogbits-wrpll-cln28hpc.h"
41 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
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| /openbmc/linux/drivers/clk/analogbits/ |
| H A D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
8 * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
10 * integrates this PLL; thus the register structure and programming
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
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| /openbmc/qemu/include/hw/misc/ |
| H A D | aspeed_scu.h | 9 * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
84 * arch/arm/mach-aspeed/include/mach/regs-scu.h
86 * Copyright (C) 2012-2020 ASPEED Technology Inc.
97 * SCU08 Clock Selection Register
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
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| /openbmc/u-boot/board/freescale/s32v234evb/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
13 * Select the clock reference for required pll.
14 * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
15 * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
17 static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) in select_pll_source_clk() argument
23 /* select the pll clock source */ in select_pll_source_clk()
32 /* The clock frequency for the source clock is unknown */ in select_pll_source_clk()
33 return -1; in select_pll_source_clk()
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| /openbmc/u-boot/arch/m68k/cpu/mcf532x/ |
| H A D | speed.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
7 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
19 /* PLL min/max specifications */
49 /* Get the value of the current system clock */
53 pll_t *pll = (pll_t *)(MMAP_PLL); in get_sys_clock() local
57 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { in get_sys_clock()
58 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
67 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 /* Tegra clock control functions */
25 * Note that no Tegra clock register actually uses all of bits 31:28 as
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
40 /* PLL stabilization delay in usec */
43 /* return the current oscillator clock frequency */
46 /* return the clk_m frequency */
50 * Start PLL using the provided configuration parameters.
52 * @param id clock id
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| /openbmc/linux/drivers/clk/bcm/ |
| H A D | clk-iproc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
22 /* PLL that requires gating through ASIU */
25 /* PLL that has fractional part of the NDIV */
29 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
36 * Some PLLs require the PLL SW override bit to be set before changes can be
37 * applied to the PLL
42 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
43 * the PLL control register
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| H A D | clk-iproc-armpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
66 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
99 * Determine the mdiv (post divider) based on the frequency ID being used.
100 * There are 4 sources that can be used to derive the output clock rate:
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| /openbmc/linux/drivers/iio/frequency/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Frequency
5 # Clock Distribution device drivers
6 # Phase-Locked Loop (PLL) frequency synthesizers
10 menu "Frequency Synthesizers DDS/PLL"
12 menu "Clock Generator/Distribution"
15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
19 Clock Generator. The driver provides direct access via sysfs.
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
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| /openbmc/linux/include/uapi/linux/ |
| H A D | timex.h | 28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
35 * Revised status codes and structures for external clock and PPS
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
62 * syscall interface - used (mainly by NTP daemon)
63 * to discipline kernel clock oscillator
68 __kernel_long_t freq; /* frequency offset (scaled ppm) */
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| /openbmc/linux/arch/x86/kernel/ |
| H A D | tsc_msr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * TSC frequency enumeration via MSR
14 #include <asm/intel-family.h>
19 #define MAX_NUM_FREQS 16 /* 4 bits to select the frequency */
22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
23 * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
26 * unclear if the root PLL outputs are used directly by the CPU clock PLL or
27 * if there is another PLL in between.
28 * This does not matter though, we can model the chain of PLLs as a single PLL
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| /openbmc/linux/drivers/clk/meson/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Clock support for Amlogic platforms"
52 bool "Meson8 SoC Clock controller support"
62 Support for the clock controller on AmLogic S802 (Meson8),
64 want peripherals and CPU frequency scaling to work.
67 tristate "GXBB and GXL SoC clock controllers support"
79 Support for the clock controller on AmLogic S905 devices, aka gxbb.
80 Say Y if you want peripherals and CPU frequency scaling to work.
83 tristate "AXG SoC clock controllers support"
94 Support for the clock controller on AmLogic A113D devices, aka axg.
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