| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | pinctrl-single.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Controller with a Single Register for One or More Pins
10 - Tony Lindgren <tony@atomide.com>
13 Some pin controller devices use a single register for one or more pins. The
14 range of pin control registers can vary from one to many for each controller
16 kind of pin controller instances.
21 - enum:
[all …]
|
| H A D | pinmux-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Multiplexing Node
10 - Linus Walleij <linus.walleij@linaro.org>
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
[all …]
|
| H A D | atmel,at91-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
11 common pinctrl bindings used by client devices, including the meaning of the
12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
[all …]
|
| H A D | ste,nomadik.txt | 4 - compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
5 "stericsson,stn8815-pinctrl"
6 - nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
7 (these have the register ranges used by the pin controller).
8 - prcm: phandle to the PRCMU managing the back end of this pin controller
10 Please refer to pinctrl-bindings.txt in this directory for details of the
11 common pinctrl bindings used by client devices, including the meaning of the
12 phrase "pin configuration node".
14 ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
16 pin, a group, or a list of pins or groups. This configuration can include the
[all …]
|
| H A D | lantiq,pinctrl-falcon.txt | 4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
9 common pinctrl bindings used by client devices, including the meaning of the
10 phrase "pin configuration node".
12 Lantiq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those group(s), and two pin configuration parameters:
16 pull-up and open-drain
22 other words, a subnode that lists a mux function but no pin configuration
[all …]
|
| H A D | bitmain,bm1880-pinctrl.txt | 1 Bitmain BM1880 Pin Controller
3 This binding describes the pin controller found in the BM1880 SoC.
7 - compatible: Should be "bitmain,bm1880-pinctrl"
8 - reg: Offset and length of pinctrl space in SCTRL.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
11 common pinctrl bindings used by client devices, including the meaning of the
12 phrase "pin configuration node".
14 The pin configuration nodes act as a container for an arbitrary number of
16 pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
17 includes pinmux and various pin configuration parameters, such as pull-up,
[all …]
|
| H A D | actions,s700-pinctrl.txt | 1 Actions Semi S700 Pin Controller
3 This binding describes the pin controller found in the S700 SoC.
7 - compatible: Should be "actions,s700-pinctrl"
8 - reg: Should contain the register base address and size of
9 the pin controller.
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
[all …]
|
| H A D | qcom,apq8084-pinctrl.txt | 6 - compatible:
9 Definition: must be "qcom,apq8084-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
29 Definition: must be 2. Specifying the pin number and flags, as defined
30 in <dt-bindings/interrupt-controller/irq.h>
[all …]
|
| H A D | actions,s900-pinctrl.txt | 1 Actions Semi S900 Pin Controller
3 This binding describes the pin controller found in the S900 SoC.
7 - compatible: Should be "actions,s900-pinctrl"
8 - reg: Should contain the register base address and size of
9 the pin controller.
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
[all …]
|
| H A D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
14 common pinctrl bindings used by client devices.
16 The node of mxs pin controller acts as a container for an arbitrary number of
[all …]
|
| H A D | canaan,k210-fpioa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
13 The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA)
15 48 IO pins of the SoC. Pin function configuration is performed on
16 a per-pin basis.
20 const: canaan,k210-fpioa
29 - description: Controller reference clock source
[all …]
|
| H A D | marvell,mvebu-pinctrl.txt | 1 * Marvell SoC pinctrl core driver for mpp
3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
7 Please refer to pinctrl-bindings.txt in this directory for details of the
8 common pinctrl bindings used by client devices, including the meaning of the
9 phrase "pin configuration node".
11 A Marvell SoC pin configuration node is a node of a group of pins which can
15 Required properties for pinctrl driver:
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
19 Required properties for pin configuration node:
[all …]
|
| /openbmc/linux/drivers/pinctrl/intel/ |
| H A D | pinctrl-tangier.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Tangier pinctrl functions
17 #include <linux/pinctrl/pinctrl.h>
19 #include "pinctrl-intel.h"
28 * struct tng_family - Tangier pin family description
30 * @pin_base: Starting pin of pins in this family
47 .npins = (e) - (s) + 1, \
54 .npins = (e) - (s) + 1, \
59 * struct tng_pinctrl - Tangier pinctrl private structure
62 * @pctldesc: Pin controller description
[all …]
|
| H A D | pinctrl-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Core pinctrl/GPIO driver for Intel GPIO controllers
19 #include <linux/pinctrl/pinctrl.h>
26 * struct intel_pingroup - Description about group of pins
27 * @grp: Generic data of the pin group (name and pins)
29 * @modes: If not %NULL this will hold mode for each pin in @pins
38 * struct intel_function - Description about a function
39 * @func: Generic data of the pin function (name and groups of pins)
48 * struct intel_padgroup - Hardware pad group information
50 * @base: Starting pin of this group
[all …]
|
| /openbmc/linux/drivers/pinctrl/nomadik/ |
| H A D | pinctrl-nomadik.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/pinctrl/pinctrl.h>
32 .pin = pin_num,\
66 * Used to reference an Other alternate-C function.
77 * struct prcm_gpio_altcx - Other alternate-C function
78 * @used: other alternate-C function availability
89 * struct prcm_gpio_altcx_pin_desc - Other alternate-C pin
90 * @pin: The pin number
91 * @altcx: array of other alternate-C[1-4] functions
94 unsigned short pin; member
[all …]
|
| H A D | pinctrl-abx500.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
34 * struct abx500_function - ABx500 pinctrl mux function
35 * @name: The name of the function, exported to pinctrl core.
36 * @groups: An array of pin groups that may select this function.
46 * struct abx500_pingroup - describes a ABx500 pin group
47 * @name: the name of this specific pin group
48 * @pins: an array of discrete physical pins used in this group, taken
49 * from the driver-local pin enumeration space
50 * @num_pins: the number of pins in this group array, i.e. the number of
51 * elements in .pins so we can iterate over that array
[all …]
|
| /openbmc/linux/drivers/pinctrl/ |
| H A D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
17 #include <linux/pinctrl/machine.h>
24 struct pinctrl;
30 * struct pinctrl_dev - pin control class device
31 * @node: node to include this pin controller in the global pin controller list
32 * @desc: the pin controller descriptor supplied when initializing this pin
[all …]
|
| /openbmc/linux/drivers/pinctrl/qcom/ |
| H A D | pinctrl-qdf2xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * GPIO and pin control functions on this SOC are handled by the "TLMM"
6 * device. The driver which controls this device is pinctrl-msm.c. Each
8 * with pinctrl-msm.c. This means that all TLMM drivers are pin control
11 * This pin control driver is intended to be used only an ACPI-enabled
12 * system. As such, UEFI will handle all pin control configuration, so
13 * this driver does not provide pin control functions. It is effectively
14 * a GPIO-only driver. The alternative is to duplicate the GPIO code of
15 * pinctrl-msm.c into another driver.
20 #include <linux/pinctrl/pinctrl.h>
[all …]
|
| /openbmc/linux/drivers/pinctrl/samsung/ |
| H A D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
16 #include <linux/pinctrl/pinctrl.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
25 * enum pincfg_type - possible pin configuration types supported.
27 * @PINCFG_TYPE_DAT: Pin value configuration.
30 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
[all …]
|
| /openbmc/linux/include/linux/pinctrl/ |
| H A D | pinctrl.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Interface the pinctrl subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
30 * struct pingroup - provides information on pingroup
32 * @pins: an array of pins in the pingroup
50 * struct pinctrl_pin_desc - boards/machines provide information on their
52 * @number: unique pin number from the global pin number space
53 * @name: a name for this pin
54 * @drv_data: driver-defined per-pin data. pinctrl core does not touch this
[all …]
|
| H A D | machine.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Machine interface for the pinctrl subsystem.
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
16 #include <linux/pinctrl/pinctrl-state.h>
27 * struct pinctrl_map_mux - mapping table content for MAP_TYPE_MUX_GROUP
39 * struct pinctrl_map_configs - mapping table content for MAP_TYPE_CONFIGS_*
40 * @group_or_pin: the name of the pin or group whose configuration parameters
42 * @configs: a pointer to an array of config parameters/values to program into
43 * hardware. Each individual pin controller defines the format and meaning
[all …]
|
| /openbmc/linux/drivers/pinctrl/bcm/ |
| H A D | pinctrl-nsp-mux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
10 * gpio_a (8 - 11)
11 * +----------
13 * gpio_a (8-11) | gpio_b (0 - 3)
14 * ------------------------+-------+----------
16 * | pwm (0 - 3)
17 * +----------
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/pinctrl/pinconf.h>
[all …]
|
| /openbmc/linux/Documentation/driver-api/ |
| H A D | pin-control.rst | 2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
[all …]
|
| /openbmc/u-boot/drivers/pinctrl/exynos/ |
| H A D | pinctrl-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Exynos pinctrl driver common code.
12 #include "pinctrl-exynos.h"
17 * exynos_pinctrl_setup_peri: setup pinctrl for a peripheral.
18 * conf: soc specific pin configuration data array
19 * num_conf: number of configurations in the conf array.
20 * base: base address of the pin controller.
35 /* given a pin-name, return the address of pin config registers */
37 u32 *pin) in pin_to_bank_base() argument
40 const struct samsung_pin_ctrl *pin_ctrl = priv->pin_ctrl; in pin_to_bank_base()
[all …]
|
| /openbmc/u-boot/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #include <dm/pinctrl.h>
16 #include <asm/arch-armada8k/soc-info.h>
17 #include "pinctrl-mvebu.h"
31 * To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux.
34 * - Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer,
35 * - Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller
36 * If pin function is set to eMMC/SD, then configure the eMMC/SD PHY
39 void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func) in mvebu_pinctl_emmc_set_mux() argument
41 const void *blob = gd->fdt_blob; in mvebu_pinctl_emmc_set_mux()
[all …]
|