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/openbmc/u-boot/drivers/pinctrl/meson/
H A Dpinctrl-meson-gxl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
12 #include <dt-bindings/gpio/meson-gxl-gpio.h>
14 #include "pinctrl-meson-gx.h"
19 PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
20 PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
21 PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
23 static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
24 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
25 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
[all …]
H A Dpinctrl-meson-gxbb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
12 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
14 #include "pinctrl-meson-gx.h"
19 PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
20 PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
21 PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
23 static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
24 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
25 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
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/openbmc/linux/drivers/gpio/
H A Dgpio-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
168 static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset) in gpreg_read() argument
170 return __raw_readl(group->reg_base + offset); in gpreg_read()
173 static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset) in gpreg_write() argument
175 __raw_writel(val, group->reg_base + offset); in gpreg_write()
178 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, in __set_gpio_dir_p012() argument
179 unsigned pin, int input) in __set_gpio_dir_p012() argument
182 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
183 group->gpio_grp->dir_clr); in __set_gpio_dir_p012()
185 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
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/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and GPIO controller
3 Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
6 GPIO and pin controller:
7 ------------------------
11 Refer to pinctrl-bindings.txt in this directory for details of the
13 of the phrase "pin configuration node".
17 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
19 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
21 - reg: The first set of registers is for pinctrl/GPIO and the second
23 - interrupts: list of interrupts used by the GPIO
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
18 of the phrase "pin configuration node".
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
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H A Dfsl,mxs-pinctrl.txt1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
18 a group of pins, and only affects those parameters that are explicitly listed.
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H A Dcnxt,cx92755-pinctrl.txt1 Conexant Digicolor CX92755 General Purpose Pin Mapping
3 This document describes the device tree binding of the pin mapping hardware
7 === Pin Controller Node ===
11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
22 compatible = "cnxt,cx92755-pinctrl";
24 gpio-controller;
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H A Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Multiplexing Node
10 - Linus Walleij <linus.walleij@linaro.org>
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP pin controller
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <linux/firmware/xlnx-zynqmp.h>
20 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-utils.h"
47 * struct zynqmp_pmux_function - a pinmux function
48 * @name: Name of the pin mux function
49 * @groups: List of pin groups for this function
52 * This structure holds information about pin control function
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H A Dpinmux.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin muxing portions of the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
24 #include <linux/radix-tree.h>
38 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
44 !ops->get_functions_count || in pinmux_check_ops()
45 !ops->get_function_name || in pinmux_check_ops()
46 !ops->get_function_groups || in pinmux_check_ops()
47 !ops->set_mux) { in pinmux_check_ops()
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H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
30 * struct pinctrl_dev - pin control class device
31 * @node: node to include this pin controller in the global pin controller list
32 * @desc: the pin controller descriptor supplied when initializing this pin
34 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
36 * @pin_group_tree: optionally each pin group can be stored in this radix tree
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
51 /* Global list of pin control devices (struct pinctrl_dev) */
54 /* List of pin controller handles (struct pinctrl) */
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
77 return pctldev->desc->name; in pinctrl_dev_get_name()
83 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
89 return pctldev->driver_data; in pinctrl_dev_get_drvdata()
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H A Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
19 #include "pinctrl-equilibrium.h"
21 #define PIN_NAME_FMT "io-%d"
32 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
33 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
34 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
45 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
47 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
48 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
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H A Dpinctrl-lantiq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinctrl-lantiq.c
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
17 #include "pinctrl-lantiq.h"
22 return info->num_grps; in ltq_get_group_count()
29 if (selector >= info->num_grps) in ltq_get_group_name()
31 return info->grps[selector].name; in ltq_get_group_name()
40 if (selector >= info->num_grps) in ltq_get_group_pins()
41 return -EINVAL; in ltq_get_group_pins()
42 *pins = info->grps[selector].pins; in ltq_get_group_pins()
[all …]
H A Dpinconf.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin config portions of the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
27 const struct pinconf_ops *ops = pctldev->desc->confops; in pinconf_check_ops()
30 if (!ops->pin_config_set && !ops->pin_config_group_set) { in pinconf_check_ops()
31 dev_err(pctldev->dev, in pinconf_check_ops()
33 return -EINVAL; in pinconf_check_ops()
40 if (!map->data.configs.group_or_pin) { in pinconf_validate_map()
41 pr_err("failed to register map %s (%d): no group/pin given\n", in pinconf_validate_map()
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/openbmc/linux/drivers/pinctrl/meson/
H A Dpinctrl-meson8-pmx.c1 // SPDX-License-Identifier: GPL-2.0-only
9 /* For this first generation of pinctrl driver every pinmux group can be
11 * a given pin are disabled the pin acts as a GPIO.
18 #include "pinctrl-meson.h"
19 #include "pinctrl-meson8-pmx.h"
22 * meson8_pmx_disable_other_groups() - disable other groups using a given pin
24 * @pc: meson pin controller device
25 * @pin: number of the pin
26 * @sel_group: index of the selected group, or -1 if none
28 * The function disables all pinmux groups using a pin except the
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/openbmc/u-boot/drivers/pinctrl/
H A Dpinctrl-generic.c1 // SPDX-License-Identifier: GPL-2.0+
14 * pinctrl_pin_name_to_selector() - return the pin selector for a pin
16 * @dev: pin controller device
17 * @pin: the pin name to look up
18 * @return: pin selector, or negative error code on failure
20 static int pinctrl_pin_name_to_selector(struct udevice *dev, const char *pin) in pinctrl_pin_name_to_selector() argument
25 if (!ops->get_pins_count || !ops->get_pin_name) { in pinctrl_pin_name_to_selector()
27 return -ENOSYS; in pinctrl_pin_name_to_selector()
30 npins = ops->get_pins_count(dev); in pinctrl_pin_name_to_selector()
32 /* See if this pctldev has this pin */ in pinctrl_pin_name_to_selector()
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpinmux.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2014
14 /* The pullup/pulldown state of a pin group */
21 /* Defines whether a pin group is tristated or in normal operation */
76 /* Defines a pin group cfg's low-power mode select */
82 PMUX_LPMD_NONE = -1,
87 /* Defines whether a pin group cfg's schmidt is enabled or not */
91 PMUX_SCHMT_NONE = -1,
96 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
100 PMUX_HSM_NONE = -1,
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/openbmc/linux/drivers/pinctrl/aspeed/
H A Dpinmux-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * functions. The SoC function enabled on a pin is determined on a priority
12 * basis where a given pin can provide a number of different signal types.
14 * The signal active on a pin is described by both a priority level and
16 * bits. Some difficulty arises as the pin's function bit masks for each
21 * read-only).
23 * SoC Multi-function Pin Expression Examples
24 * ------------------------------------------
30 * D6 is a pin with a single function (beside GPIO); a high priority signal
34 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
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/openbmc/linux/Documentation/driver-api/
H A Dpin-control.rst2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
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/openbmc/linux/drivers/pinctrl/pxa/
H A Dpinctrl-pxa2xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell PXA2xx family pin control
15 #include <linux/pinctrl/pinconf-generic.h>
21 #include "../pinctrl-utils.h"
22 #include "pinctrl-pxa2xx.h"
28 return pctl->ngroups; in pxa2xx_pctrl_get_groups_count()
35 struct pxa_pinctrl_group *group = pctl->groups + tgroup; in pxa2xx_pctrl_get_group_name() local
37 return group->name; in pxa2xx_pctrl_get_group_name()
46 struct pxa_pinctrl_group *group = pctl->groups + tgroup; in pxa2xx_pctrl_get_group_pins() local
48 *pins = (unsigned *)&group->pin; in pxa2xx_pctrl_get_group_pins()
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/openbmc/linux/drivers/pinctrl/intel/
H A Dpinctrl-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
27 * @grp: Generic data of the pin group (name and pins)
28 * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
29 * @modes: If not %NULL this will hold mode for each pin in @pins
38 * struct intel_function - Description about a function
39 * @func: Generic data of the pin function (name and groups of pins)
48 * struct intel_padgroup - Hardware pad group information
50 * @base: Starting pin of this group
51 * @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE).
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/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
44 * Bank type for non-alive type. Bit fields:
64 /* pin banks of exynos5433 pin-controller - ALIVE */
66 /* Must start with EINTG banks, ordered by EINT group number. */
78 /* pin banks of exynos5433 pin-controller - AUD */
80 /* Must start with EINTG banks, ordered by EINT group number. */
85 /* pin banks of exynos5433 pin-controller - CPIF */
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/openbmc/u-boot/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
37 /* List these attributes which could be modified for the pin */
51 /* Group the pins by the driving current */
62 * struct mtk_pin_field - the structure that holds the information of the field
63 * used to describe the attribute for the pin
78 * struct mtk_pin_field_calc - the structure that holds the range providing
80 * @s_pin: the start pin within the range
81 * @e_pin: the end pin within the range
90 * pin
104 * struct mtk_pin_reg_calc - the structure that holds all ranges used to
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/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #include <linux/pinctrl/pinconf-generic.h>
14 #include "mtk-eint.h"
36 struct pinctrl_pin_desc pin; member
43 .pin = _pin, \
61 #define SET_ADDR(x, y) (x + (y->devdata->port_align))
62 #define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1))
67 unsigned pin; member
71 * struct mtk_drv_group_desc - Provide driving group data.
72 * @max_drv: The maximum current of this group.
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