| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-mvebu-pic.c | 36 static void mvebu_pic_reset(struct mvebu_pic *pic) in mvebu_pic_reset() argument
39 writel(0, pic->base + PIC_MASK); in mvebu_pic_reset()
40 writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE); in mvebu_pic_reset()
45 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_eoi_irq() local
47 writel(1 << d->hwirq, pic->base + PIC_CAUSE); in mvebu_pic_eoi_irq()
52 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_mask_irq() local
55 reg = readl(pic->base + PIC_MASK); in mvebu_pic_mask_irq()
57 writel(reg, pic->base + PIC_MASK); in mvebu_pic_mask_irq()
62 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_unmask_irq() local
65 reg = readl(pic->base + PIC_MASK); in mvebu_pic_unmask_irq()
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| H A D | irq-or1k-pic.c | 13 /* OR1K PIC implementation */
48 * There are two oddities with the OR1200 PIC implementation:
66 .name = "or1k-PIC-level",
76 .name = "or1k-PIC-edge",
88 .name = "or1200-PIC",
123 struct or1k_pic_dev *pic = d->host_data; in or1k_map() local
125 irq_set_chip_and_handler(irq, &pic->chip, pic->handle); in or1k_map()
126 irq_set_status_flags(irq, pic->flags); in or1k_map()
137 * This sets up the IRQ domain for the PIC built in to the OpenRISC
142 struct or1k_pic_dev *pic) in or1k_pic_init() argument
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| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | interrupts.c | 24 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; in interrupt_init_cpu() local
28 * The POST word is stored in the PIC's TFRR register which gets in interrupt_init_cpu()
29 * cleared when the PIC is reset. Save it off so we can restore it in interrupt_init_cpu()
35 out_be32(&pic->gcr, MPC85xx_PICGCR_RST); in interrupt_init_cpu()
36 while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) in interrupt_init_cpu()
38 out_be32(&pic->gcr, MPC85xx_PICGCR_M); in interrupt_init_cpu()
39 in_be32(&pic->gcr); in interrupt_init_cpu()
47 pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ in interrupt_init_cpu()
48 debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1); in interrupt_init_cpu()
50 pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ in interrupt_init_cpu()
[all …]
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| /openbmc/u-boot/arch/powerpc/cpu/mpc86xx/ |
| H A D | interrupts.c | 28 volatile ccsr_pic_t *pic = &immr->im_pic; in interrupt_init_cpu() local
32 * The POST word is stored in the PIC's TFRR register which gets in interrupt_init_cpu()
33 * cleared when the PIC is reset. Save it off so we can restore it in interrupt_init_cpu()
39 pic->gcr = MPC86xx_PICGCR_RST; in interrupt_init_cpu()
40 while (pic->gcr & MPC86xx_PICGCR_RST) in interrupt_init_cpu()
42 pic->gcr = MPC86xx_PICGCR_MODE; in interrupt_init_cpu()
51 pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */ in interrupt_init_cpu()
52 debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1); in interrupt_init_cpu()
54 pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ in interrupt_init_cpu()
55 debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2); in interrupt_init_cpu()
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| /openbmc/linux/arch/mips/boot/dts/loongson/ |
| H A D | ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 { label
14 compatible = "loongson,pch-pic-1.0";
18 loongson,pic-base-vec = <0>;
25 interrupt-parent = <&pic>;
33 interrupt-parent = <&pic>;
43 interrupt-parent = <&pic>;
53 interrupt-parent = <&pic>;
63 interrupt-parent = <&pic>;
89 interrupt-parent = <&pic>;
100 interrupt-parent = <&pic>;
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| /openbmc/qemu/hw/intc/ |
| H A D | heathrow_pic.c | 2 * Heathrow PIC support (OldWorld PowerMac)
33 static inline int heathrow_check_irq(HeathrowPICState *pic) in heathrow_check_irq() argument
35 return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask; in heathrow_check_irq()
53 HeathrowPICState *pic; in heathrow_write() local
60 pic = &s->pics[n]; in heathrow_write()
63 pic->mask = value; in heathrow_write()
68 value &= ~pic->level_triggered; in heathrow_write()
69 pic->events &= ~value; in heathrow_write()
81 HeathrowPICState *pic; in heathrow_read() local
89 pic = &s->pics[n]; in heathrow_read()
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | open-pic.txt | 1 * Open PIC Binding
4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [1] and is a superset of that
13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
20 as an Open PIC. No property value shall be defined.
31 - pic-no-reset: The presence of this property indicates that the PIC
55 * An Open PIC interrupt controller
57 mpic: pic@40000 {
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| H A D | loongson,pch-pic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
7 title: Loongson PCH PIC Controller
19 const: loongson,pch-pic-1.0
24 loongson,pic-base-vec:
27 to PCH PIC.
40 - loongson,pic-base-vec
49 pic: interrupt-controller@10000000 {
50 compatible = "loongson,pch-pic-1.0";
54 loongson,pic-base-vec = <64>;
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| H A D | opencores,or1k-pic.txt | 5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7 edge triggered interrupt lines or "opencores,or1200-pic" for machines
10 "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
20 compatible = "opencores,or1k-pic-level";
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| H A D | marvell,armada-8k-pic.txt | 1 Marvell Armada 7K/8K PIC Interrupt controller
4 This is the Device Tree binding for the PIC, a secondary interrupt
9 - compatible: should be "marvell,armada-8k-pic"
13 - reg: the register area for the PIC interrupt controller
19 pic: interrupt-controller@3f0100 {
20 compatible = "marvell,armada-8k-pic";
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| /openbmc/linux/arch/powerpc/platforms/cell/ |
| H A D | spider-pic.c | 64 static void __iomem *spider_get_irq_config(struct spider_pic *pic, in spider_get_irq_config() argument
67 return pic->regs + TIR_CFGA + 8 * src; in spider_get_irq_config()
72 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_unmask_irq() local
73 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_unmask_irq()
80 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_mask_irq() local
81 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_mask_irq()
88 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_ack_irq() local
101 out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); in spider_ack_irq()
107 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_set_irq_type() local
109 void __iomem *cfg = spider_get_irq_config(pic, hw); in spider_set_irq_type()
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| /openbmc/linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu2_hw_mpeg2_dec.c | 99 const struct v4l2_ctrl_mpeg2_picture *pic) in rockchip_vpu2_mpeg2_dec_set_buffers() argument
104 switch (pic->picture_coding_type) { in rockchip_vpu2_mpeg2_dec_set_buffers()
106 backward_addr = hantro_get_ref(ctx, pic->backward_ref_ts); in rockchip_vpu2_mpeg2_dec_set_buffers()
109 forward_addr = hantro_get_ref(ctx, pic->forward_ref_ts); in rockchip_vpu2_mpeg2_dec_set_buffers()
120 if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD) in rockchip_vpu2_mpeg2_dec_set_buffers()
130 if (pic->picture_structure == V4L2_MPEG2_PIC_FRAME || in rockchip_vpu2_mpeg2_dec_set_buffers()
131 pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B || in rockchip_vpu2_mpeg2_dec_set_buffers()
132 (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD && in rockchip_vpu2_mpeg2_dec_set_buffers()
133 pic->flags & V4L2_MPEG2_PIC_TOP_FIELD) || in rockchip_vpu2_mpeg2_dec_set_buffers()
134 (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD && in rockchip_vpu2_mpeg2_dec_set_buffers()
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| H A D | hantro_g1_mpeg2_dec.c | 96 const struct v4l2_ctrl_mpeg2_picture *pic) in hantro_g1_mpeg2_dec_set_buffers() argument
101 switch (pic->picture_coding_type) { in hantro_g1_mpeg2_dec_set_buffers()
103 backward_addr = hantro_get_ref(ctx, pic->backward_ref_ts); in hantro_g1_mpeg2_dec_set_buffers()
106 forward_addr = hantro_get_ref(ctx, pic->forward_ref_ts); in hantro_g1_mpeg2_dec_set_buffers()
117 if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD) in hantro_g1_mpeg2_dec_set_buffers()
127 if (pic->picture_structure == V4L2_MPEG2_PIC_FRAME || in hantro_g1_mpeg2_dec_set_buffers()
128 pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B || in hantro_g1_mpeg2_dec_set_buffers()
129 (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD && in hantro_g1_mpeg2_dec_set_buffers()
130 pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST) || in hantro_g1_mpeg2_dec_set_buffers()
131 (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD && in hantro_g1_mpeg2_dec_set_buffers()
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| /openbmc/linux/arch/m68k/virt/ |
| H A D | ints.c | 34 * 6 goldfish-pic for CPU IRQ #1 to IRQ #6
35 * CPU IRQ #1 -> PIC #1
38 * CPU IRQ #2 -> PIC #2
40 * CPU IRQ #3 -> PIC #3
42 * CPU IRQ #4 -> PIC #4
44 * CPU IRQ #5 -> PIC #5
46 * CPU IRQ #6 -> PIC #6
53 static u32 gfpic_read(int pic, int reg) in gfpic_read() argument
55 void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio + in gfpic_read()
56 pic * 0x1000); in gfpic_read()
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | v3-v360epc-pci.txt | 39 interrupt-parent = <&pic>;
56 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
57 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
58 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
59 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
61 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
62 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
64 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
66 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
[all …]
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| /openbmc/linux/drivers/staging/media/sunxi/cedrus/ |
| H A D | cedrus_mpeg2.c | 54 const struct v4l2_ctrl_mpeg2_picture *pic; in cedrus_mpeg2_setup() local
64 pic = run->mpeg2.picture; in cedrus_mpeg2_setup()
91 reg = VE_DEC_MPEG_MP12HDR_SLICE_TYPE(pic->picture_coding_type); in cedrus_mpeg2_setup()
92 reg |= VE_DEC_MPEG_MP12HDR_F_CODE(0, 0, pic->f_code[0][0]); in cedrus_mpeg2_setup()
93 reg |= VE_DEC_MPEG_MP12HDR_F_CODE(0, 1, pic->f_code[0][1]); in cedrus_mpeg2_setup()
94 reg |= VE_DEC_MPEG_MP12HDR_F_CODE(1, 0, pic->f_code[1][0]); in cedrus_mpeg2_setup()
95 reg |= VE_DEC_MPEG_MP12HDR_F_CODE(1, 1, pic->f_code[1][1]); in cedrus_mpeg2_setup()
96 reg |= VE_DEC_MPEG_MP12HDR_INTRA_DC_PRECISION(pic->intra_dc_precision); in cedrus_mpeg2_setup()
97 reg |= VE_DEC_MPEG_MP12HDR_INTRA_PICTURE_STRUCTURE(pic->picture_structure); in cedrus_mpeg2_setup()
98 reg |= VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST); in cedrus_mpeg2_setup()
[all …]
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-networking/cyrus-sasl/cyrus-sasl/ |
| H A D | debian_patches_0014_avoid_pic_overwrite.diff | 6 Description: This patch makes sure the non-PIC version of libsasldb.a, which
7 is created out of non-PIC objects, is not going to overwrite the PIC version,
8 which is created out of PIC objects. The PIC version is placed in .libs, and
9 the non-PIC version in the current directory. This ensures that both non-PIC
10 and PIC versions are available in the correct locations.
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| /openbmc/linux/arch/arm/boot/dts/arm/ |
| H A D | integratorap.dts | 157 pic: pic@14000000 { label
169 interrupt-parent = <&pic>;
186 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
187 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
188 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
189 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
191 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
192 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
193 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
194 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
[all …]
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| /openbmc/linux/arch/xtensa/boot/dts/ |
| H A D | virt.dts | 8 interrupt-parent = <&pic>;
37 pic: pic { label
38 compatible = "cdns,xtensa-pic";
64 0x0000 0x0 0x0 0x1 &pic 0x0 0x1
65 0x0800 0x0 0x0 0x1 &pic 0x1 0x1
66 0x1000 0x0 0x0 0x1 &pic 0x2 0x1
67 0x1800 0x0 0x0 0x1 &pic 0x3 0x1
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| /openbmc/qemu/hw/arm/ |
| H A D | xlnx-versal.c | 67 static void versal_create_apu_gic(Versal *s, qemu_irq *pic) in versal_create_apu_gic() argument
136 pic[i] = qdev_get_gpio_in(gicdev, i); in versal_create_apu_gic()
169 static void versal_create_uarts(Versal *s, qemu_irq *pic) in versal_create_uarts() argument
189 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); in versal_create_uarts()
194 static void versal_create_canfds(Versal *s, qemu_irq *pic) in versal_create_canfds() argument
221 sysbus_connect_irq(sbd, 0, pic[irqs[i]]); in versal_create_canfds()
226 static void versal_create_usbs(Versal *s, qemu_irq *pic) in versal_create_usbs() argument
245 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]); in versal_create_usbs()
251 static void versal_create_gems(Versal *s, qemu_irq *pic) in versal_create_gems() argument
276 qdev_connect_gpio_out(DEVICE(or_irq), 0, pic[irqs[i]]); in versal_create_gems()
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| H A D | realview.c | 86 qemu_irq pic[64]; in realview_init() local
205 pic[n] = qdev_get_gpio_in(dev, n); in realview_init()
215 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); in realview_init()
217 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); in realview_init()
218 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); in realview_init()
220 pl011_create(0x10009000, pic[12], serial_hd(0)); in realview_init()
221 pl011_create(0x1000a000, pic[13], serial_hd(1)); in realview_init()
222 pl011_create(0x1000b000, pic[14], serial_hd(2)); in realview_init()
223 pl011_create(0x1000c000, pic[15], serial_hd(3)); in realview_init()
232 sysbus_connect_irq(busdev, 0, pic[24]); in realview_init()
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| /openbmc/linux/arch/powerpc/boot/dts/ |
| H A D | tqm8xx.dts | 39 interrupt-parent = <&PIC>;
73 interrupt-parent = <&PIC>;
85 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: pic@0 { label
124 compatible = "fsl,mpc860-pic", "fsl,pq1-pic";
156 CPM_PIC: pic@930 {
161 interrupt-parent = <&PIC>;
163 compatible = "fsl,mpc860-cpm-pic",
164 "fsl,cpm1-pic";
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| /openbmc/linux/arch/powerpc/platforms/52xx/ |
| H A D | lite5200_pm.c | 15 static struct mpc52xx_intr __iomem *pic; variable
78 pic = mbar + 0x500; in lite5200_pm_prepare()
100 _memcpy_fromio(&spic, pic, sizeof(*pic)); in lite5200_save_regs()
188 /* PIC */ in lite5200_restore_regs()
189 out_be32(&pic->per_pri1, spic.per_pri1); in lite5200_restore_regs()
190 out_be32(&pic->per_pri2, spic.per_pri2); in lite5200_restore_regs()
191 out_be32(&pic->per_pri3, spic.per_pri3); in lite5200_restore_regs()
193 out_be32(&pic->main_pri1, spic.main_pri1); in lite5200_restore_regs()
194 out_be32(&pic->main_pri2, spic.main_pri2); in lite5200_restore_regs()
196 out_be32(&pic->enc_status, spic.enc_status); in lite5200_restore_regs()
[all …]
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| /openbmc/qemu/hw/nubus/ |
| H A D | nubus-virtio-mmio.c | 39 /* Goldfish PIC */ in nubus_virtio_mmio_realize()
40 sbd = SYS_BUS_DEVICE(&s->pic); in nubus_virtio_mmio_realize()
47 qdev_get_gpio_in_named(dev, "pic-input-irq", 0)); in nubus_virtio_mmio_realize()
62 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(&s->pic), i)); in nubus_virtio_mmio_realize()
71 object_initialize_child(obj, "pic", &s->pic, TYPE_GOLDFISH_PIC); in nubus_virtio_mmio_init()
79 /* Input from goldfish PIC */ in nubus_virtio_mmio_init()
81 "pic-input-irq", 1); in nubus_virtio_mmio_init()
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| /openbmc/openbmc/poky/meta/recipes-extended/groff/files/ |
| H A D | 0001-build-Fix-Savannah-64681-webpage.ps-deps.patch | 25 @@ -346,6 +346,9 @@ doc/pic.ps: $(doc_srcdir)/pic.ms eqn pic tbl
27 && $(DOC_GROFF) -pet -Tps -ms $(doc_srcdir)/pic.ms >$@
35 @@ -365,11 +368,12 @@ doc/pic.html: $(doc_srcdir)/pic.ms
37 $(doc_srcdir)/pic.ms > pic.html
|