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/openbmc/linux/drivers/usb/phy/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * phy.c -- USB phy handling
5 * Copyright (C) 2004-2013 Texas Instruments
15 #include <linux/usb/phy.h>
17 /* Default current range by charger type. */
33 struct usb_phy *phy; member
52 enum usb_phy_type type) in __usb_find_phy() argument
54 struct usb_phy *phy = NULL; in __usb_find_phy() local
56 list_for_each_entry(phy, list, head) { in __usb_find_phy()
57 if (phy->type != type) in __usb_find_phy()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
[all …]
H A Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 stdout-path = "serial0:115200n8";
36 shunt-resistor = <1000>;
67 #address-cells = <2>;
68 #size-cells = <1>;
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H A Dfsl-ls2080a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
15 #include "fsl-ls2080a.dtsi"
16 #include "fsl-ls208xa-rdb.dtsi"
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
24 stdout-path = "serial1:115200n8";
29 phy-handle = <&mdio2_phy1>;
30 phy-connection-type = "10gbase-r";
34 phy-handle = <&mdio2_phy2>;
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dtestmode.c1 // SPDX-License-Identifier: ISC
8 [MT76_TM_ATTR_RESET] = { .type = NLA_FLAG },
9 [MT76_TM_ATTR_STATE] = { .type = NLA_U8 },
10 [MT76_TM_ATTR_TX_COUNT] = { .type = NLA_U32 },
11 [MT76_TM_ATTR_TX_LENGTH] = { .type = NLA_U32 },
12 [MT76_TM_ATTR_TX_RATE_MODE] = { .type = NLA_U8 },
13 [MT76_TM_ATTR_TX_RATE_NSS] = { .type = NLA_U8 },
14 [MT76_TM_ATTR_TX_RATE_IDX] = { .type = NLA_U8 },
15 [MT76_TM_ATTR_TX_RATE_SGI] = { .type = NLA_U8 },
16 [MT76_TM_ATTR_TX_RATE_LDPC] = { .type = NLA_U8 },
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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
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H A Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
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H A Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
H A Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
H A Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
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H A Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fqd {
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Torrent SD0801 PHY
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
12 PHY also supports multilink multiprotocol combinations including protocols
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
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H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Sierra PHY
10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 USB HS PHY controller
11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
12 switch. It controls PHY configuration and status, and the UTMI+ switch that
13 selects either OTG or HOST controller for the second PHY port. It also sets
19 |_ PHY port#1 _________________ HOST controller
22 |_ PHY port#2 ----| |________________
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
15 sets, clock and PHY.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
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/openbmc/u-boot/drivers/phy/allwinner/
H A Dphy-sun4i-usb.c2 * Allwinner sun4i USB PHY driver
8 * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
10 * SPDX-License-Identifier: GPL-2.0+
17 #include <generic-phy.h>
18 #include <phy-sun4i-usb.h>
37 /* Private Control Bits for Each PHY */
82 enum sun4i_usb_phy_type type; member
136 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len) in sun4i_usb_phy_write() argument
138 struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev); in sun4i_usb_phy_write()
139 struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id]; in sun4i_usb_phy_write()
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/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
68 * Returns one's complement 8-bit sum.
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
91 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_read_i2c_combined_generic_int()
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) in ixgbe_read_i2c_combined_generic_int()
105 return -EBUSY; in ixgbe_read_i2c_combined_generic_int()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: GPL-2.0
6 #include "armada-8040.dtsi"
9 model = "ClearFog-GT-8K";
10 compatible = "solidrun,clearfog-gt-8k",
14 stdout-path = "serial0:115200n8";
28 simple-bus {
29 compatible = "simple-bus";
31 reg_usb3h0_vbus: usb3-vbus0 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
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/openbmc/linux/drivers/phy/mediatek/
H A Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
16 #include <linux/phy/phy.h>
19 #include "phy-mtk-io.h"
21 /* u2 phy banks */
26 /* u3 phy shared banks */
30 /* u3 phy banks */
85 struct phy *phy; member
87 struct clk *ref_clk; /* reference clock of anolog phy */
89 u32 type; member
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dxusb-padctl.h7 * tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
8 * @type: the type of PHY to obtain
10 * The type of PHY varies between SoC generations. Typically there are XUSB,
12 * value of type can usually be directly parsed from a device tree.
14 * Return: a pointer to the PHY or NULL if no such PHY exists
16 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
19 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
20 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
21 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
22 int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy);

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