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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sdx55-pcie-ep
17 - qcom,sm8450-pcie-ep
18 - items:
19 - const: qcom,sdx65-pcie-ep
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/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-qcom-ep.c1 // SPDX-License-Identifier: GPL-2.0
26 #include "pcie-designware.h"
144 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
154 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
159 * @perst_map: PERST regmap
162 * @reset: PERST# GPIO
169 * @perst_en: Flag for PERST enable
170 * @perst_sep_en: Flag for PERST separation enable
173 * @perst_irq: PERST# IRQ
205 struct dw_pcie *pci = &pcie_ep->pci; in qcom_pcie_ep_core_reset()
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H A Dpci-keystone.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
31 #include "pcie-designware.h"
59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
110 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
145 return readl(ks_pcie->va_app_base + offset); in ks_pcie_app_readl()
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H A Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
36 #include "pcie-designware.h"
45 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
109 /* PCIe Port Logic registers (memory-mapped) */
122 /* PHY registers (not memory-mapped) */
159 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && in imx6_pcie_grp_offset()
160 imx6_pcie->drvdata->variant != IMX8MQ_EP && in imx6_pcie_grp_offset()
161 imx6_pcie->drvdata->variant != IMX8MM && in imx6_pcie_grp_offset()
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-388-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include "armada-388-clearfog.dtsi"
13 compatible = "solidrun,clearfog-a1", "marvell,armada388",
17 internal-regs {
27 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-0 = <&rear_button_pins>;
36 pinctrl-names = "default";
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H A Darmada-388-clearfog.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include "armada-388.dtsi"
9 #include "armada-38x-solidrun-microsom.dtsi"
13 /* So that mvebu u-boot can update the MAC addresses */
20 stdout-path = "serial0:115200n8";
23 reg_3p3v: regulator-3p3v {
24 compatible = "regulator-fixed";
25 regulator-name = "3P3V";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
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/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_pcie2.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
134 /* PCIE gen2 config regs */
151 #define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
152 #define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
153 #define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
154 #define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
156 #define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
157 #define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
/openbmc/u-boot/arch/arm/dts/
H A Darmada-388-clearfog.dts11 * This file is dual-licensed: you can use it either under the terms
49 /dts-v1/;
50 #include <dt-bindings/input/input.h>
51 #include <dt-bindings/gpio/gpio.h>
52 #include "armada-388.dtsi"
53 #include "armada-38x-solidrun-microsom.dtsi"
57 compatible = "solidrun,clearfog-a1", "marvell,armada388",
61 /* So that mvebu u-boot can update the MAC addresses */
71 stdout-path = "serial0:115200n8";
74 reg_3p3v: regulator-3p3v {
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/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
93 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
99 #define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */
106 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
107 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
144 /* Half-duplex collision counts */
179 /* disable clear of sticky ULP on PERST */
181 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */
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/openbmc/linux/drivers/pci/controller/
H A Dpcie-mediatek-gen3.c1 // SPDX-License-Identifier: GPL-2.0
61 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
65 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
69 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
95 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
104 * struct mtk_msi_set - MSI information for each set
116 * struct mtk_gen3_pcie - PCIe port information
188 * mtk_pcie_config_tlp_header() - Configure a configuration TLP header
199 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_config_tlp_header()
203 bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); in mtk_pcie_config_tlp_header()
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H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
152 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
154 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
244 /* This is the base pointer for interrupt status/set/clr regs */
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H A Dpcie-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
74 /* PCIe V2 per-port registers */
127 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
145 * struct mtk_pcie_soc - differentiate between host generations
165 * struct mtk_pcie_port - PCIe port information
209 * struct mtk_pcie - PCIe host information
213 * @free_ck: free-run reference clock
214 * @mem: non-prefetchable memory resource
216 * @soc: pointer to SoC-dependent operations
230 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerdown()
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H A Dpci-mvebu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
120 struct resource regs; member
130 writel(val, port->base + reg); in mvebu_writel()
135 return readl(port->base + reg); in mvebu_readl()
140 return port->io_target != -1 && port->io_attr != -1; in mvebu_has_ioport()
199 * BAR[0] -> internal registers (needed for MSI)
200 * BAR[1] -> covers all DRAM banks
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H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
256 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
317 } regs; member
365 struct resource regs; member
378 writel(value, pcie->afi + offset); in afi_writel()
383 return readl(pcie->afi + offset); in afi_readl()
389 writel(value, pcie->pads + offset); in pads_writel()
394 return readl(pcie->pads + offset); in pads_readl()
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/openbmc/linux/drivers/misc/cxl/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <asm/pnv-pci.h>
89 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
90 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
161 dev_info(&dev->dev, "dump_cxl_config_space\n"); in dump_cxl_config_space()
164 dev_info(&dev->dev, "BAR0: %#.8x\n", val); in dump_cxl_config_space()
166 dev_info(&dev->dev, "BAR1: %#.8x\n", val); in dump_cxl_config_space()
168 dev_info(&dev->dev, "BAR2: %#.8x\n", val); in dump_cxl_config_space()
170 dev_info(&dev->dev, "BAR3: %#.8x\n", val); in dump_cxl_config_space()
172 dev_info(&dev->dev, "BAR4: %#.8x\n", val); in dump_cxl_config_space()
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/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx6-pins.h>
12 #include <asm/mach-imx/mxc_i2c.h>
13 #include <asm/mach-imx/iomux-v3.h>
14 #include <asm/mach-imx/sata.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/video.h>
126 /* PERST# */
132 gd->ram_size = 2048ul * 1024 * 1024; in dram_init()
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/openbmc/linux/drivers/misc/genwqe/
H A Dcard_base.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
26 #include <linux/dma-mapping.h>
37 MODULE_AUTHOR("Joerg-Stephan Vogt <jsvogt@de.ibm.com>");
59 /* Initial SR-IOV bring-up image */
108 * genwqe_devnode() - Set default access mode for genwqe devices.
110 * @mode: Carrier to pass-back given mode (permissions)
128 * genwqe_dev_alloc() - Create and prepare a new card descriptor
142 return ERR_PTR(-ENODEV); in genwqe_dev_alloc()
146 return ERR_PTR(-ENOMEM); in genwqe_dev_alloc()
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
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H A Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
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H A Dqcom-sdx55.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sdx55.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
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/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_self_test.c1 // SPDX-License-Identifier: GPL-2.0
30 u32 imm1; /* 1st value in predicate condition, left-to-right */
31 u32 imm2; /* 2nd value in predicate condition, left-to-right */
32 u32 imm3; /* 3rd value in predicate condition, left-to-right */
33 u32 imm4; /* 4th value in predicate condition, left-to-right */
36 /* struct representing self test record - a single test */
54 return (args->val1 == args->imm1); in peq()
59 return (args->val1 != args->imm1); in pneq()
64 return ((args->val1 & args->imm1) != args->imm2); in pand_neq()
69 return (((args->val1 & args->imm1) != args->imm2) && in pand_neq_x2()
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