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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dsony,imx415.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Riesch <michael.riesch@wolfvision.net>
12 description: |-
14 solid-state image sensor with a square pixel array and 8.46 M effective
16 1.8 V triple power supply, and has low power consumption.
18 available via CSI-2 serial data output (two or four lanes).
21 - $ref: ../video-interface-devices.yaml#
34 avdd-supply:
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H A Dsony,imx296.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony IMX296 1/2.8-Inch CMOS Image Sensor
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The Sony IMX296 is a 1/2.9-Inch active pixel type CMOS Solid-state image
16 features a global shutter with variable charge-integration time. It is
17 programmable through I2C and 4-wire interfaces. The sensor output is
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dite,it6505.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Allen Chen <allen.chen@ite.com.tw>
13 The IT6505 is a high-performance DisplayPort 1.1a transmitter,
16 and ensures robust transmission of high-quality uncompressed video
27 transmission of high-definition content. Users of the IT6505 need not
37 ovdd-supply:
40 pwr18-supply:
47 reset-gpios:
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/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
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/openbmc/linux/drivers/media/i2c/
H A Dimx335.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <media/v4l2-ctrls.h>
16 #include <media/v4l2-fwnode.h>
17 #include <media/v4l2-subdev.h>
59 * struct imx335_reg - imx335 sensor register
69 * struct imx335_reg_list - imx335 sensor register list
79 "avdd", /* Analog (2.9V) supply */
80 "ovdd", /* Digital I/O (1.8V) supply */
81 "dvdd", /* Digital Core (1.2V) supply */
85 * struct imx335_mode - imx335 sensor mode structure
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H A Dimx296.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
190 "ovdd",
224 ret = regmap_raw_read(sensor->regmap, addr & IMX296_REG_ADDR_MASK, data, in imx296_read()
240 ret = regmap_raw_write(sensor->regmap, addr & IMX296_REG_ADDR_MASK, in imx296_write()
243 dev_err(sensor->dev, "%u-bit write to 0x%04x failed: %d\n", in imx296_write()
257 ret = regulator_bulk_enable(ARRAY_SIZE(sensor->supplies), in imx296_power_on()
258 sensor->supplies); in imx296_power_on()
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H A Dimx415.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
104 "ovdd",
110 * describe MIPI CSI-2 speed. This driver uses lane rates wherever possible
124 /* INCK Settings - includes all lane rate and INCK dependent registers */
203 /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
219 /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
235 /* all-pixel 4-lane 891 Mbps 30 Hz mode */
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