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/openbmc/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dreset.c5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
8 * COPYING in the main directory of this source tree, or the
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
[all …]
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
[all …]
/openbmc/u-boot/lib/efi_loader/
H A Defi_net.c1 // SPDX-License-Identifier: GPL-2.0+
20 * The notification function of this event is called in every timer cycle
30 * struct efi_net_obj - EFI object representing a network interface
34 * @net_mode: status of the network interface
36 * @pxe_mode: status of the PXE base code protocol
47 * efi_net_start() - start the network interface
49 * This function implements the Start service of the
65 goto out; in efi_net_start()
68 if (this->mode->state != EFI_NETWORK_STOPPED) in efi_net_start()
71 this->mode->state = EFI_NETWORK_STARTED; in efi_net_start()
[all …]
/openbmc/linux/arch/arm/mach-meson/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/of.h>
13 #include <linux/reset.h>
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
106 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", in meson8b_smp_prepare_cpus()
107 "amlogic,meson8b-smp-sram"); in meson8b_smp_prepare_cpus()
112 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", in meson8_smp_prepare_cpus()
113 "amlogic,meson8-smp-sram"); in meson8_smp_prepare_cpus()
121 * system without power-cycling, or when taking the CPU offline and in meson_smp_begin_secondary_boot()
[all …]
/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_watchdog.robot3 Documentation Module to test out of band IPMI watchdog functionality.
22 [Documentation] Execute out of band set/get do not log bit for watchdog timer.
33 [Documentation] Execute out of band set/get stop/resume timer stop bit for watchdog timer.
44 [Documentation] Execute out of band set/get timer use bits for watchdog timer.
60 Test IPMI Watchdog Timer Pre-Timeout Interrupt Bits
61 [Documentation] Execute out of band set/get pre-timeout interrupt bits for watchdog timer.
62 [Tags] Test_IPMI_Watchdog_Timer_Pre-Timeout_Interrupt_Bits
72 [Documentation] Execute out of band set/get timer timeout bits for watchdog timer.
87 [Documentation] Execute out of band set/get timer timeout flag bits for watchdog timer.
111 ${IPMI_RAW_CMD['Watchdog']['Set'][63]} ['on'] Hard reset
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dimg,i2s-out.txt5 - compatible : Compatible list, must contain "img,i2s-out"
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device
11 - clocks : Contains an entry for each entry in clock-names
13 - clock-names : Must include the following entries:
17 - dmas: Contains an entry for each entry in dma-names.
19 - dma-names: Must include the following entry:
22 - img,i2s-channels : Number of I2S channels instantiated in the I2S out block
24 - resets: Contains a phandle to the I2S out reset signal
26 - reset-names: Contains the reset signal name "rst"
[all …]
H A Dimg,spdif-out.txt5 - compatible : Compatible list, must contain "img,spdif-out"
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device
11 - dmas: Contains an entry for each entry in dma-names.
13 - dma-names: Must include the following entry:
16 - clocks : Contains an entry for each entry in clock-names.
18 - clock-names : Includes the following entries:
22 - resets: Contains a phandle to the spdif out reset signal
24 - reset-names: Contains the reset signal name "rst"
28 - interrupts : Contains the parallel out interrupt, if present
[all …]
H A Dimg,parallel-out.txt5 - compatible : Compatible list, must contain "img,parallel-out".
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device.
11 - dmas: Contains an entry for each entry in dma-names.
13 - dma-names: Must include the following entry:
16 - clocks : Contains an entry for each entry in clock-names.
18 - clock-names : Includes the following entries:
22 - resets: Contains a phandle to the parallel out reset signal
24 - reset-names: Contains the reset signal name "rst"
28 - interrupts : Contains the parallel out interrupt, if present
[all …]
/openbmc/linux/drivers/firewire/
H A Dcore-card.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2005-2007 Kristian Hoegsberg <krh@bitplanet.net>
8 #include <linux/crc-itu-t.h>
12 #include <linux/firewire-constants.h>
37 dev_name(card->device), &vaf); \
82 * IEEE-1394 specifies a default SPLIT_TIMEOUT value of 800 cycles (100 ms),
96 * Initialize contents of config rom buffer. On the OHCI in generate_config_rom()
100 * sure the contents of bus info block in host memory matches in generate_config_rom()
108 BIB_LINK_SPEED(card->link_speed) | in generate_config_rom()
109 BIB_GENERATION(card->config_rom_generation++ % 14 + 2) | in generate_config_rom()
[all …]
/openbmc/linux/drivers/firmware/efi/
H A Dcapsule.c1 // SPDX-License-Identifier: GPL-2.0
25 static int efi_reset_type = -1;
34 * efi_capsule_pending - has a capsule been passed to the firmware?
35 * @reset_type: store the type of EFI reset if capsule is pending
38 * firmware we need to perform a specific type of reset. If a capsule is
39 * pending return the reset type in @reset_type.
41 * This function will race with callers of efi_capsule_update(), for
47 * A non-racy use is from platform reboot code because we use
63 * Whitelist of EFI capsule flags that we support.
74 * efi_capsule_supported - does the firmware support the capsule?
[all …]
/openbmc/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_common.c7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
27 { .compatible = "fsl,mpc5200-xlb", },
28 { .compatible = "mpc5200-xlb", },
32 { .compatible = "fsl,mpc5200-immr", },
33 { .compatible = "fsl,mpc5200b-immr", },
34 { .compatible = "simple-bus", },
73 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
74 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
79 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 /* Set of oscillator frequencies supported in the internal API. */
25 * Note that no Tegra clock register actually uses all of bits 31:28 as
28 * safe to pretend that the mux field extends all the way to the end of the
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
86 * @returns 0 if ok, -1 on error (invalid clock id)
114 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
[all …]
/openbmc/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
9 * Some parts of the code were originally released under BSD license:
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
18 * * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
22 * copyright notice, this list of conditions and the following
26 * * Neither the name of Cavium Networks nor the names of
40 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
[all …]
/openbmc/linux/drivers/misc/cxl/
H A Dhcalls.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 * This is straight out of PAPR, but replacing some of the compound fields with
26 * The 'flags' parameter regroups the various bit-fields
59 * cxl_h_detach_process - Detach a process element from a coherent
65 * cxl_h_reset_afu - Perform a reset to the coherent platform function.
70 * cxl_h_suspend_process - Suspend a process from being executed
71 * Parameter1 = process-token as returned from H_ATTACH_CA_PROCESS when
77 * cxl_h_resume_process - Resume a process to be executed
78 * Parameter1 = process-token as returned from H_ATTACH_CA_PROCESS when
84 * cxl_h_read_error_state - Reads the error state of the coherent
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/modules/hdcp/
H A Dhdcp.c4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
8 * and/or sell copies of the Software, and to permit persons to whom the
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
31 struct mod_hdcp_trace *trace = &hdcp->connection.trace; in push_error_status()
33 if (trace->error_count < MAX_NUM_OF_ERROR_TRACE) { in push_error_status()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_reset.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2018 Intel Corporation
40 struct drm_i915_file_private *file_priv = ctx->file_priv; in client_mark_guilty()
51 prev_hang = xchg(&file_priv->hang_timestamp, jiffies); in client_mark_guilty()
56 atomic_add(score, &file_priv->ban_score); in client_mark_guilty()
58 drm_dbg(&ctx->i915->drm, in client_mark_guilty()
60 ctx->name, score, in client_mark_guilty()
61 atomic_read(&file_priv->ban_score)); in client_mark_guilty()
72 if (intel_context_is_closed(rq->context)) in mark_guilty()
76 ctx = rcu_dereference(rq->context->gem_context); in mark_guilty()
[all …]
/openbmc/linux/kernel/trace/
H A Dtrace_selftest.c1 // SPDX-License-Identifier: GPL-2.0
12 switch (entry->type) { in trace_valid_entry()
32 while ((event = ring_buffer_consume(buf->buffer, cpu, NULL, NULL))) { in trace_test_buffer_cpu()
36 * The ring buffer is a size of trace_buf_size, if in trace_test_buffer_cpu()
46 entry->type); in trace_test_buffer_cpu()
56 return -1; in trace_test_buffer_cpu()
68 /* Don't allow flipping of max traces now */ in trace_test_buffer()
70 arch_spin_lock(&buf->tr->max_lock); in trace_test_buffer()
72 cnt = ring_buffer_entries(buf->buffer); in trace_test_buffer()
88 arch_spin_unlock(&buf->tr->max_lock); in trace_test_buffer()
[all …]
/openbmc/linux/arch/arm64/kvm/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
6 * Derived from arch/arm/kvm/reset.c
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
37 * ARMv8 Reset Values
65 * Don't even try to make use of vector lengths that in kvm_arm_init_sve()
79 return -EINVAL; in kvm_vcpu_enable_sve()
81 vcpu->arch.sve_max_vl = kvm_sve_max_vl; in kvm_vcpu_enable_sve()
95 * vcpu->arch.sve_state as necessary.
104 vl = vcpu->arch.sve_max_vl; in kvm_vcpu_finalize_sve()
[all …]
/openbmc/docs/designs/
H A Dpower-recovery.md11 Modern computer systems have a feature, automated power-on recovery, which in
13 power to the system. If the system had a black out (i.e. power was completely
19 occur. For example, some systems have op-panels, and on these op-panels there
20 can be a pin hole reset. This is a manual mechanism for the user to force a hard
21 reset to the BMC in situations where it is hung or not responding. In these
25 During blackout scenarios, system owners may have a set of services they need
30 A brownout is another scenario that commonly utilizes automated power-on
33 be retained. On some systems, it's desired to utilize the automated power-on
38 brownout scenario. A UPS has a limited amount of power so it's main purpose is
39 to handle brief power interruptions or to allow for an orderly shutdown of the
[all …]
/openbmc/linux/arch/arm/mach-bcm/
H A Dbcm63xx_pmb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/reset/bcm63xx_pmb.h>
12 #include <linux/of.h>
97 return -ENODEV; in bcm63xx_pmb_get_resources()
100 ret = of_parse_phandle_with_args(dn, "resets", "#reset-cells", in bcm63xx_pmb_get_resources()
108 pr_err("reset-controller does not conform to reset-cells\n"); in bcm63xx_pmb_get_resources()
109 return -EINVAL; in bcm63xx_pmb_get_resources()
115 return -ENOMEM; in bcm63xx_pmb_get_resources()
118 /* We do not need the number of zones */ in bcm63xx_pmb_get_resources()
142 * value since we will use it later for CPU de-assert once done with in bcm63xx_pmb_power_on_cpu()
[all …]
/openbmc/linux/Documentation/driver-api/
H A Dreset.rst1 .. SPDX-License-Identifier: GPL-2.0-only
4 Reset controller API
10 Reset controllers are central units that control the reset signals to multiple
12 The reset controller API is split into two parts:
13 the `consumer driver interface <#consumer-driver-interface>`__ (`API reference
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
15 over their reset input signals, and the `reset controller driver interface
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
18 controller devices to register their reset controls to provide them to the
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2014
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <asm/arch-tegra/pmc.h>
17 /* Tegra114-specific CPU init code */
26 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ in enable_cpu_power_rail()
31 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), in enable_cpu_power_rail()
35 writel(reg, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
38 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); in enable_cpu_power_rail()
39 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); in enable_cpu_power_rail()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_phy.c1 // SPDX-License-Identifier: GPL-2.0
8 * igc_check_reset_block - Check if PHY reset is blocked
11 * Read the PHY management control register and check whether a PHY reset
12 * is blocked. If a reset is not blocked return 0, otherwise
26 * igc_get_phy_id - Retrieve the PHY ID and revision
34 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
40 goto out; in igc_get_phy_id()
42 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
44 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
[all …]
/openbmc/linux/drivers/scsi/cxlflash/
H A Dmain.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 * process_cmd_err() - command error handler
44 struct afu *afu = cmd->parent; in process_cmd_err()
45 struct cxlflash_cfg *cfg = afu->parent; in process_cmd_err()
46 struct device *dev = &cfg->dev->dev; in process_cmd_err()
50 ioasa = &(cmd->sa); in process_cmd_err()
52 if (ioasa->rc.flags & SISL_RC_FLAGS_UNDERRUN) { in process_cmd_err()
53 resid = ioasa->resid; in process_cmd_err()
59 if (ioasa->rc.flags & SISL_RC_FLAGS_OVERRUN) { in process_cmd_err()
62 scp->result = (DID_ERROR << 16); in process_cmd_err()
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dprminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
36 * Populates the base addresses of the _prm_bases
37 * array used for read/write of prm module registers.
75 /* Read-modify-write a register in PRM. Caller must lock */
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
93 * @shift: register bit shift corresponding to the reset line to check
97 * -EINVAL upon parameter error.
[all …]

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