Home
last modified time | relevance | path

Searched full:osc (Results 1 – 25 of 432) sorted by relevance

12345678910>>...18

/openbmc/linux/drivers/clk/at91/
H A Dsckc.c70 struct clk_slow_osc *osc = to_clk_slow_osc(hw); in clk_slow_osc_prepare() local
71 void __iomem *sckcr = osc->sckcr; in clk_slow_osc_prepare()
74 if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) in clk_slow_osc_prepare()
77 writel(tmp | osc->bits->cr_osc32en, sckcr); in clk_slow_osc_prepare()
80 udelay(osc->startup_usec); in clk_slow_osc_prepare()
82 usleep_range(osc->startup_usec, osc->startup_usec + 1); in clk_slow_osc_prepare()
89 struct clk_slow_osc *osc = to_clk_slow_osc(hw); in clk_slow_osc_unprepare() local
90 void __iomem *sckcr = osc->sckcr; in clk_slow_osc_unprepare()
93 if (tmp & osc->bits->cr_osc32byp) in clk_slow_osc_unprepare()
96 writel(tmp & ~osc->bits->cr_osc32en, sckcr); in clk_slow_osc_unprepare()
[all …]
H A Dclk-main.c73 struct clk_main_osc *osc = to_clk_main_osc(hw); in clk_main_osc_prepare() local
74 struct regmap *regmap = osc->regmap; in clk_main_osc_prepare()
96 struct clk_main_osc *osc = to_clk_main_osc(hw); in clk_main_osc_unprepare() local
97 struct regmap *regmap = osc->regmap; in clk_main_osc_unprepare()
113 struct clk_main_osc *osc = to_clk_main_osc(hw); in clk_main_osc_is_prepared() local
114 struct regmap *regmap = osc->regmap; in clk_main_osc_is_prepared()
128 struct clk_main_osc *osc = to_clk_main_osc(hw); in clk_main_osc_save_context() local
130 osc->pms.status = clk_main_osc_is_prepared(hw); in clk_main_osc_save_context()
137 struct clk_main_osc *osc = to_clk_main_osc(hw); in clk_main_osc_restore_context() local
139 if (osc->pms.status) in clk_main_osc_restore_context()
[all …]
/openbmc/linux/drivers/clk/versatile/
H A Dclk-vexpress-osc.c23 #define to_vexpress_osc(osc) container_of(osc, struct vexpress_osc, hw) argument
28 struct vexpress_osc *osc = to_vexpress_osc(hw); in vexpress_osc_recalc_rate() local
31 regmap_read(osc->reg, 0, &rate); in vexpress_osc_recalc_rate()
39 struct vexpress_osc *osc = to_vexpress_osc(hw); in vexpress_osc_round_rate() local
41 if (osc->rate_min && rate < osc->rate_min) in vexpress_osc_round_rate()
42 rate = osc->rate_min; in vexpress_osc_round_rate()
44 if (osc->rate_max && rate > osc->rate_max) in vexpress_osc_round_rate()
45 rate = osc->rate_max; in vexpress_osc_round_rate()
53 struct vexpress_osc *osc = to_vexpress_osc(hw); in vexpress_osc_set_rate() local
55 return regmap_write(osc->reg, 0, rate); in vexpress_osc_set_rate()
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
58 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
73 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
74 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
75 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
76 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx7d.c44 static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
49 static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
54 static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
58 static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
62 static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
67 static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
72 static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
83 static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
88 static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
93 static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk",
[all …]
H A Dclk-imx5.c66 static const char *lp_apm_sel[] = { "osc", };
82 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
83 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
84 static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_…
86 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
87 static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_…
89 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
110 "osc", "ckih1",
119 static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
120 static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
[all …]
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra-fixed.c30 struct clk *clk, *osc; in tegra_osc_clk_init() local
53 osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq); in tegra_osc_clk_init()
54 *dt_clk = osc; in tegra_osc_clk_init()
59 clk = clk_register_fixed_factor(NULL, "osc_div2", "osc", in tegra_osc_clk_init()
67 clk = clk_register_fixed_factor(NULL, "osc_div4", "osc", in tegra_osc_clk_init()
76 clk = clk_register_fixed_factor(NULL, "clk_m", "osc", in tegra_osc_clk_init()
87 clk = clk_register_fixed_factor(NULL, "pll_ref", "osc", in tegra_osc_clk_init()
/openbmc/openbmc/poky/bitbake/lib/bb/fetch2/
H A Dosc.py7 Bitbake "Fetch" implementation for osc (Opensuse build service client).
23 class Osc(FetchMethod): class
29 Check to see if a given url can be fetched with osc.
31 return ud.type in ['osc']
39 # Create paths to osc checkouts
40 oscdir = d.getVar("OSCDIR") or (d.getVar("DL_DIR") + "/osc")
64 basecmd = d.getVar("FETCHCMD_osc") or "/usr/bin/env osc"
84 raise FetchError("Invalid osc command %s" % command, ud.url)
97 raise FetchError("Unable to parse osc response", ud.url)
107 return "osc:%s%s.%s.%s" % (ud.host, slash_re.sub(".", ud.path), name, rev)
/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-clock.dtsi35 osc: oscillator { label
44 clocks = <&osc>;
54 clocks = <&osc>;
66 clocks = <&osc>;
78 clocks = <&osc>;
88 clocks = <&osc>;
100 clocks = <&osc>;
110 clocks = <&osc>;
121 clocks = <&osc>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx7d-clock.yaml35 - description: 32k osc
36 - description: 24m osc
41 - const: osc
63 clocks = <&ckil>, <&osc>;
64 clock-names = "ckil", "osc";
H A Dimx6ul-clock.yaml32 - description: 32k osc
33 - description: 24m osc
40 - const: osc
65 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
66 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
H A Dimx6sll-clock.yaml32 - description: 32k osc
33 - description: 24m osc
40 - const: osc
65 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
66 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
H A Dimx6sx-clock.yaml32 - description: 32k osc
33 - description: 24m osc
42 - const: osc
69 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
70 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
H A Dimxrt1050-clock.yaml29 description: 24m osc
33 const: osc
56 clocks = <&osc>;
57 clock-names = "osc";
H A Dimx8m-clock.yaml62 - description: 32k osc
63 - description: 25m osc
64 - description: 27m osc
82 - description: 32k osc
83 - description: 24m osc
H A Dstarfive,jh7110-aoncrg.yaml49 - const: osc
60 - const: osc
95 clocks = <&osc>, <&gmac0_rmii_refin>,
101 clock-names = "osc", "gmac0_rmii_refin",
H A Dallwinner,sun4i-a10-osc-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml#
20 const: allwinner,sun4i-a10-osc-clk
45 compatible = "allwinner,sun4i-a10-osc-clk";
H A Dstarfive,jh7110-syscrg.yaml51 - const: osc
66 - const: osc
104 clocks = <&osc>, <&gmac1_rmii_refin>,
110 clock-names = "osc", "gmac1_rmii_refin",
/openbmc/u-boot/drivers/clk/
H A Dclk_vexpress_osc.c18 u8 osc; member
30 data = CLK_FUNCTION | priv->osc; in vexpress_osc_clk_get_rate()
53 buffer[0] = CLK_FUNCTION | priv->osc; in vexpress_osc_clk_set_rate()
90 priv->osc = values[1]; in vexpress_osc_clk_probe()
92 priv->osc, priv->rate_min, priv->rate_max); in vexpress_osc_clk_probe()
98 { .compatible = "arm,vexpress-osc", },
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-cygnus-clock.dtsi38 osc: oscillator { label
48 clocks = <&osc>;
74 clocks = <&osc>;
101 clocks = <&osc>;
110 clocks = <&osc>;
121 clocks = <&osc>;
129 clocks = <&osc>;
/openbmc/linux/drivers/clocksource/
H A Dtimer-tegra186.c90 struct clocksource osc; member
333 osc); in tegra186_timer_osc_read()
340 tegra->osc.name = "osc"; in tegra186_timer_osc_init()
341 tegra->osc.rating = 300; in tegra186_timer_osc_init()
342 tegra->osc.read = tegra186_timer_osc_read; in tegra186_timer_osc_init()
343 tegra->osc.mask = CLOCKSOURCE_MASK(32); in tegra186_timer_osc_init()
344 tegra->osc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in tegra186_timer_osc_init()
346 return clocksource_register_hz(&tegra->osc, 38400000); in tegra186_timer_osc_init()
421 dev_err(dev, "failed to register OSC counter: %d\n", err); in tegra186_timer_probe()
443 clocksource_unregister(&tegra->osc); in tegra186_timer_probe()
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2-clock.dtsi35 osc: oscillator { label
47 clocks = <&osc>;
60 clocks = <&osc>;
74 clocks = <&osc>;
102 clocks = <&osc>;
/openbmc/linux/arch/xtensa/boot/dts/
H A Dxtfpga.dtsi23 clocks = <&osc>;
51 osc: main-oscillator { label
66 clocks = <&osc>;
75 clocks = <&osc>;
95 clocks = <&osc>;
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts150 compatible = "arm,vexpress-osc";
159 compatible = "arm,vexpress-osc";
168 compatible = "arm,vexpress-osc";
177 compatible = "arm,vexpress-osc";
186 compatible = "arm,vexpress-osc";
195 compatible = "arm,vexpress-osc";
/openbmc/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-core.c125 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference) in mcp251xfd_get_osc_str() argument
127 switch (~osc & osc_reference & in mcp251xfd_get_osc_str()
232 u32 con = 0, con_reqop, osc = 0; in __mcp251xfd_chip_set_mode() local
267 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); in __mcp251xfd_chip_set_mode()
271 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n", in __mcp251xfd_chip_set_mode()
272 con, osc); in __mcp251xfd_chip_set_mode()
279 …"Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\… in __mcp251xfd_chip_set_mode()
282 con, osc); in __mcp251xfd_chip_set_mode()
305 u32 osc; in mcp251xfd_chip_wait_for_osc_ready() local
308 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc, in mcp251xfd_chip_wait_for_osc_ready()
[all …]

12345678910>>...18