Home
last modified time | relevance | path

Searched +full:osc +full:- +full:bypass (Results 1 – 25 of 59) sorted by relevance

123

/openbmc/linux/drivers/clk/at91/
H A Dsckc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk-provider.h>
70 struct clk_slow_osc *osc = to_clk_slow_osc(hw); in clk_slow_osc_prepare() local
71 void __iomem *sckcr = osc->sckcr; in clk_slow_osc_prepare()
74 if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) in clk_slow_osc_prepare()
77 writel(tmp | osc->bits->cr_osc32en, sckcr); in clk_slow_osc_prepare()
80 udelay(osc->startup_usec); in clk_slow_osc_prepare()
82 usleep_range(osc->startup_usec, osc->startup_usec + 1); in clk_slow_osc_prepare()
89 struct clk_slow_osc *osc = to_clk_slow_osc(hw); in clk_slow_osc_unprepare() local
90 void __iomem *sckcr = osc->sckcr; in clk_slow_osc_unprepare()
[all …]
H A Dclk-main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
73 struct clk_main_osc *osc = to_clk_main_osc(hw); in clk_main_osc_prepare() local
74 struct regmap *regmap = osc->regmap; in clk_main_osc_prepare()
96 struct clk_main_osc *osc = to_clk_main_osc(hw); in clk_main_osc_unprepare() local
97 struct regmap *regmap = osc->regmap; in clk_main_osc_unprepare()
113 struct clk_main_osc *osc = to_clk_main_osc(hw); in clk_main_osc_is_prepared() local
114 struct regmap *regmap = osc->regmap; in clk_main_osc_is_prepared()
128 struct clk_main_osc *osc = to_clk_main_osc(hw); in clk_main_osc_save_context() local
130 osc->pms.status = clk_main_osc_is_prepared(hw); in clk_main_osc_save_context()
[all …]
H A Dat91rm9200.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
6 #include <dt-bindings/clock/at91.h>
86 bool bypass; in at91rm9200_pmc_setup() local
88 i = of_property_match_string(np, "clock-names", "slow_xtal"); in at91rm9200_pmc_setup()
94 i = of_property_match_string(np, "clock-names", "main_xtal"); in at91rm9200_pmc_setup()
109 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91rm9200_pmc_setup()
112 bypass); in at91rm9200_pmc_setup()
120 at91rm9200_pmc->chws[PMC_MAIN] = hw; in at91rm9200_pmc_setup()
128 at91rm9200_pmc->chws[PMC_PLLACK] = hw; in at91rm9200_pmc_setup()
[all …]
H A Dat91sam9g45.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
6 #include <dt-bindings/clock/at91.h>
101 bool bypass; in at91sam9g45_pmc_setup() local
103 i = of_property_match_string(np, "clock-names", "slow_clk"); in at91sam9g45_pmc_setup()
109 i = of_property_match_string(np, "clock-names", "main_xtal"); in at91sam9g45_pmc_setup()
124 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9g45_pmc_setup()
127 bypass); in at91sam9g45_pmc_setup()
135 at91sam9g45_pmc->chws[PMC_MAIN] = hw; in at91sam9g45_pmc_setup()
146 at91sam9g45_pmc->chws[PMC_PLLACK] = hw; in at91sam9g45_pmc_setup()
[all …]
H A Dat91sam9n12.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
6 #include <dt-bindings/clock/at91.h>
121 bool bypass; in at91sam9n12_pmc_setup() local
123 i = of_property_match_string(np, "clock-names", "slow_clk"); in at91sam9n12_pmc_setup()
129 i = of_property_match_string(np, "clock-names", "main_xtal"); in at91sam9n12_pmc_setup()
148 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9n12_pmc_setup()
151 bypass); in at91sam9n12_pmc_setup()
161 at91sam9n12_pmc->chws[PMC_MAIN] = hw; in at91sam9n12_pmc_setup()
172 at91sam9n12_pmc->chws[PMC_PLLACK] = hw; in at91sam9n12_pmc_setup()
[all …]
H A Dat91sam9x5.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
6 #include <dt-bindings/clock/at91.h>
143 bool bypass; in at91sam9x5_pmc_setup() local
145 i = of_property_match_string(np, "clock-names", "slow_clk"); in at91sam9x5_pmc_setup()
151 i = of_property_match_string(np, "clock-names", "main_xtal"); in at91sam9x5_pmc_setup()
170 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9x5_pmc_setup()
173 bypass); in at91sam9x5_pmc_setup()
183 at91sam9x5_pmc->chws[PMC_MAIN] = hw; in at91sam9x5_pmc_setup()
194 at91sam9x5_pmc->chws[PMC_PLLACK] = hw; in at91sam9x5_pmc_setup()
[all …]
H A Dsama5d4.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
6 #include <dt-bindings/clock/at91.h>
138 bool bypass; in sama5d4_pmc_setup() local
140 i = of_property_match_string(np, "clock-names", "slow_clk"); in sama5d4_pmc_setup()
146 i = of_property_match_string(np, "clock-names", "main_xtal"); in sama5d4_pmc_setup()
166 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in sama5d4_pmc_setup()
169 bypass); in sama5d4_pmc_setup()
188 sama5d4_pmc->chws[PMC_PLLACK] = hw; in sama5d4_pmc_setup()
194 sama5d4_pmc->chws[PMC_UTMI] = hw; in sama5d4_pmc_setup()
[all …]
H A Dsama5d3.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
6 #include <dt-bindings/clock/at91.h>
123 bool bypass; in sama5d3_pmc_setup() local
125 i = of_property_match_string(np, "clock-names", "slow_clk"); in sama5d3_pmc_setup()
131 i = of_property_match_string(np, "clock-names", "main_xtal"); in sama5d3_pmc_setup()
151 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in sama5d3_pmc_setup()
154 bypass); in sama5d3_pmc_setup()
173 sama5d3_pmc->chws[PMC_PLLACK] = hw; in sama5d3_pmc_setup()
179 sama5d3_pmc->chws[PMC_UTMI] = hw; in sama5d3_pmc_setup()
[all …]
H A Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
33 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
53 "atmel,sama5d2-clk-audio-pll-frac",
59 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
79 "atmel,sama5d2-clk-audio-pll-pad",
85 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
105 "atmel,sama5d2-clk-audio-pll-pmc",
161 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
162 name = gcknp->name; in of_sama5d2_clk_generated_setup()
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/scu.h>
24 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; in get_num_cpus()
48 * ------------------------------
55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
[all …]
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/timer.h>
66 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_bypass()
81 return &clkrst->crc_pll[clkid]; in get_pll()
100 return -1; in clock_ll_read_pll()
101 data = readl(&pll->pll_base); in clock_ll_read_pll()
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
237 * they are used as index in osc[] as entry point
414 ulong osc[NB_OSC]; member
745 (u32)priv->osc[idx], priv->osc[idx] / 1000); in stm32mp1_clk_get_fixed()
747 return priv->osc[idx]; in stm32mp1_clk_get_fixed()
752 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_id()
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
24 static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
27 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
60 static const char *uart_sels[] = { "pll3_80m", "osc", };
61 static const char *ipg_per_sels[] = { "ipg", "osc", };
62 static const char *ecspi_sels[] = { "pll3_60m", "osc", };
[all …]
H A Dclk-imxrt1050.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
12 #include <dt-bindings/clock/imxrt1050-clock.h>
16 static const char * const pll_ref_sels[] = {"osc", "dummy", };
17 static const char * const per_sels[] = {"ipg_pdof", "osc", };
26 static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
40 struct device *dev = &pdev->dev; in imxrt1050_clocks_probe()
41 struct device_node *np = dev->of_node; in imxrt1050_clocks_probe()
48 return -ENOMEM; in imxrt1050_clocks_probe()
50 clk_hw_data->num = IMXRT1050_CLK_END; in imxrt1050_clocks_probe()
51 hws = clk_hw_data->hws; in imxrt1050_clocks_probe()
[all …]
H A Dclk-imx6sl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
14 #include <dt-bindings/clock/imx6sl-clock.h>
34 static const char *step_sels[] = { "osc", "pll2_pfd2", };
39 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
43 static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
47 static const char *perclk_sels[] = { "ipg", "osc", };
55 static const char *ecspi_sels[] = { "pll3_60m", "osc", };
56 static const char *uart_sels[] = { "pll3_80m", "osc", };
60 "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot_avp.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010 - 2011
13 #include <asm/arch-tegra/ap.h>
14 #include <asm/arch-tegra/apb_misc.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/pmc.h>
17 #include <asm/arch-tegra/warmboot.h>
37 writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl); in wb_start()
55 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
57 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Datmel,at91sam9x5-sckc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/atmel,at91sam9x5-sckc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
15 - enum:
16 - atmel,at91sam9x5-sckc
17 - atmel,sama5d3-sckc
18 - atmel,sama5d4-sckc
19 - microchip,sam9x60-sckc
[all …]
H A Datmel,at91rm9200-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/atmel,at91rm9200-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
20 - items:
21 - const: atmel,at91sam9g20-pmc
22 - const: atmel,at91sam9260-pmc
23 - const: syscon
24 - items:
[all …]
/openbmc/linux/include/linux/iio/frequency/
H A Dad9523.h1 /* SPDX-License-Identifier: GPL-2.0-only */
38 * struct ad9523_channel_spec - Output channel configuration
42 * @sync_ignore_en: Ignore chip-level SYNC signal.
49 * @channel_divider: 10-bit channel divider.
106 * struct ad9523_platform_data - platform specific information
109 * @refa_diff_rcv_en: REFA differential/single-ended input selection.
110 * @refb_diff_rcv_en: REFB differential/single-ended input selection.
111 * @zd_in_diff_en: Zero Delay differential/single-ended input selection.
112 * @osc_in_diff_en: OSC differential/ single-ended input selection.
113 * @refa_cmos_neg_inp_en: REFA single-ended neg./pos. input enable.
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dscg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
122 /* SCG System OSC Control Status Register */
136 /* SCG RTC OSC Control Status Register */
181 /* 0: SPLL, 1: bypass */
187 /* 0: Sys-OSC, 1: FIRC */
272 u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */
273 u32 soscdiv; /* System OSC Divide Register */
296 u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */
/openbmc/linux/drivers/regulator/
H A Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
20 #define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
30 bool bypass; member
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm8731.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8731.c -- WM8731 ALSA SoC Audio driver
6 * Copyright 2006-12 Wolfson Microelectronics, plc
76 if (wm8731->deemph) { in wm8731_set_deemph()
79 if (abs(wm8731_deemph[i] - wm8731->playback_fs) < in wm8731_set_deemph()
80 abs(wm8731_deemph[best] - wm8731->playback_fs)) in wm8731_set_deemph()
90 dev_dbg(component->dev, "Set deemphasis %d (%dHz)\n", in wm8731_set_deemph()
102 ucontrol->value.integer.value[0] = wm8731->deemph; in wm8731_get_deemph()
112 unsigned int deemph = ucontrol->value.integer.value[0]; in wm8731_put_deemph()
116 return -EINVAL; in wm8731_put_deemph()
[all …]
/openbmc/linux/drivers/mfd/
H A Dtwl-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * twl_core.c - driver for TWL4030/TWL5030/TWL60X0/TPS659x0 PM
6 * Copyright (C) 2005-2006 Texas Instruments, Inc.
37 #include <linux/mfd/twl4030-audio.h>
39 #include "twl-core.h"
42 * The TWL4030 "Triton 2" is one of a family of a multi-function "Power
60 /* subchip/slave 0 - USB ID */
63 /* subchip/slave 1 - AUD ID */
70 /* subchip/slave 2 - AUX ID */
83 /* subchip/slave 3 - POWER ID */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
86 * @returns 0 if ok, -1 on error (invalid clock id)
143 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
145 * @param reset 1 to assert reset, 0 to de-assert
154 * Warning: This function is only for use pre-relocation. Please use
168 * @param source source clock (0-15 depending on mux_bits)
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-wb50n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module
12 model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
17 stdout-path = "serial0:115200n8";
38 clock-frequency = <32768>;
42 clock-frequency = <12000000>;
46 atmel,osc-bypass;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
52 cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>;
[all …]

123