/openbmc/linux/arch/riscv/kernel/probes/ |
H A D | simulate-insn.c | 36 bool __kprobes simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs) in simulate_jal() argument 40 * imm [20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode in simulate_jal() 45 u32 index = (opcode >> 7) & 0x1f; in simulate_jal() 51 imm = ((opcode >> 21) & 0x3ff) << 1; in simulate_jal() 52 imm |= ((opcode >> 20) & 0x1) << 11; in simulate_jal() 53 imm |= ((opcode >> 12) & 0xff) << 12; in simulate_jal() 54 imm |= ((opcode >> 31) & 0x1) << 20; in simulate_jal() 61 bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs) in simulate_jalr() argument 65 * offset[11:0] | rs1 | 010 | rd | opcode in simulate_jalr() 70 u32 imm = (opcode >> 20) & 0xfff; in simulate_jalr() [all …]
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/openbmc/linux/arch/arm64/kernel/probes/ |
H A D | simulate-insn.c | 52 static bool __kprobes check_cbz(u32 opcode, struct pt_regs *regs) in check_cbz() argument 54 int xn = opcode & 0x1f; in check_cbz() 56 return (opcode & (1 << 31)) ? in check_cbz() 60 static bool __kprobes check_cbnz(u32 opcode, struct pt_regs *regs) in check_cbnz() argument 62 int xn = opcode & 0x1f; in check_cbnz() 64 return (opcode & (1 << 31)) ? in check_cbnz() 68 static bool __kprobes check_tbz(u32 opcode, struct pt_regs *regs) in check_tbz() argument 70 int xn = opcode & 0x1f; in check_tbz() 71 int bit_pos = ((opcode & (1 << 31)) >> 26) | ((opcode >> 19) & 0x1f); in check_tbz() 76 static bool __kprobes check_tbnz(u32 opcode, struct pt_regs *regs) in check_tbnz() argument [all …]
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/openbmc/linux/arch/csky/kernel/probes/ |
H A D | simulate-insn.c | 69 simulate_br16(u32 opcode, long addr, struct pt_regs *regs) in simulate_br16() argument 72 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_br16() 76 simulate_br32(u32 opcode, long addr, struct pt_regs *regs) in simulate_br32() argument 79 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_br32() 83 simulate_bt16(u32 opcode, long addr, struct pt_regs *regs) in simulate_bt16() argument 87 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bt16() 93 simulate_bt32(u32 opcode, long addr, struct pt_regs *regs) in simulate_bt32() argument 97 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bt32() 103 simulate_bf16(u32 opcode, long addr, struct pt_regs *regs) in simulate_bf16() argument 107 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bf16() [all …]
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/openbmc/qemu/linux-user/arm/nwfpe/ |
H A D | fpa11_cpdt.c | 215 static unsigned int PerformLDF(const unsigned int opcode) in PerformLDF() argument 219 write_back = WRITE_BACK(opcode); in PerformLDF() 221 //printk("PerformLDF(0x%08x), Fd = 0x%08x\n",opcode,getFd(opcode)); in PerformLDF() 223 pBase = readRegister(getRn(opcode)); in PerformLDF() 224 if (ARM_REG_PC == getRn(opcode)) in PerformLDF() 231 if (BIT_UP_SET(opcode)) in PerformLDF() 232 pFinal += getOffset(opcode) * 4; in PerformLDF() 234 pFinal -= getOffset(opcode) * 4; in PerformLDF() 236 if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase; in PerformLDF() 238 switch (opcode & MASK_TRANSFER_LENGTH) in PerformLDF() [all …]
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H A D | fpa11_cprt.c | 30 unsigned int PerformFLT(const unsigned int opcode); 31 unsigned int PerformFIX(const unsigned int opcode); 34 PerformComparison(const unsigned int opcode); 36 unsigned int EmulateCPRT(const unsigned int opcode) in EmulateCPRT() argument 40 //printk("EmulateCPRT(0x%08x)\n",opcode); in EmulateCPRT() 42 if (opcode & 0x800000) in EmulateCPRT() 48 return PerformComparison(opcode); in EmulateCPRT() 52 switch ((opcode & 0x700000) >> 20) in EmulateCPRT() 54 case FLT_CODE >> 20: nRc = PerformFLT(opcode); break; in EmulateCPRT() 55 case FIX_CODE >> 20: nRc = PerformFIX(opcode); break; in EmulateCPRT() [all …]
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H A D | fpopcode.h | 66 abcd arithmetic opcode (TABLES 3 & 4) 188 #define MASK_CPDT 0x0c000000 /* data processing opcode */ 200 /* Get the coprocessor number from the opcode. */ 201 #define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8) argument 203 /* Get the offset from the opcode. */ 204 #define getOffset(opcode) (opcode & MASK_OFFSET) argument 207 #define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask)) argument 209 #define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD) argument 210 #define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT) argument 212 #define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) argument [all …]
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H A D | fpa11.c | 74 void SetRoundingMode(const unsigned int opcode) in SetRoundingMode() argument 82 switch (opcode & MASK_ROUNDING_MODE) in SetRoundingMode() 116 void SetRoundingPrecision(const unsigned int opcode) in SetRoundingPrecision() argument 123 switch (opcode & MASK_ROUNDING_PRECISION) { in SetRoundingPrecision() 152 /* Emulate the instruction in the opcode. */ 154 unsigned int EmulateAll(unsigned int opcode, FPA11* qfpa, CPUARMState* qregs) in EmulateAll() argument 165 cp = (opcode >> 8) & 0xf; in EmulateAll() 175 opcode, qregs[ARM_REG_PC]); in EmulateAll() 189 if (TEST_OPCODE(opcode,MASK_CPRT)) in EmulateAll() 195 nRc = EmulateCPRT(opcode); in EmulateAll() [all …]
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/openbmc/linux/arch/arm/nwfpe/ |
H A D | fpa11_cpdt.c | 212 unsigned int PerformLDF(const unsigned int opcode) in PerformLDF() argument 215 unsigned int nRc = 1, write_back = WRITE_BACK(opcode); in PerformLDF() 217 pBase = (unsigned int __user *) readRegister(getRn(opcode)); in PerformLDF() 218 if (REG_PC == getRn(opcode)) { in PerformLDF() 224 if (BIT_UP_SET(opcode)) in PerformLDF() 225 pFinal += getOffset(opcode); in PerformLDF() 227 pFinal -= getOffset(opcode); in PerformLDF() 229 if (PREINDEXED(opcode)) in PerformLDF() 234 switch (opcode & MASK_TRANSFER_LENGTH) { in PerformLDF() 236 loadSingle(getFd(opcode), pAddress); in PerformLDF() [all …]
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H A D | fpopcode.h | 57 abcd arithmetic opcode (TABLES 3 & 4) 179 #define MASK_CPDT 0x0c000000 /* data processing opcode */ 191 /* Get the coprocessor number from the opcode. */ 192 #define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8) argument 194 /* Get the offset from the opcode. */ 195 #define getOffset(opcode) (opcode & MASK_OFFSET) argument 198 #define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask)) argument 200 #define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD) argument 201 #define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT) argument 203 #define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) argument [all …]
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H A D | fpa11_cprt.c | 18 unsigned int PerformFLT(const unsigned int opcode); 19 unsigned int PerformFIX(const unsigned int opcode); 21 static unsigned int PerformComparison(const unsigned int opcode); 23 unsigned int EmulateCPRT(const unsigned int opcode) in EmulateCPRT() argument 26 if (opcode & 0x800000) { in EmulateCPRT() 31 return PerformComparison(opcode); in EmulateCPRT() 35 switch ((opcode & 0x700000) >> 20) { in EmulateCPRT() 37 return PerformFLT(opcode); in EmulateCPRT() 40 return PerformFIX(opcode); in EmulateCPRT() 44 writeFPSR(readRegister(getRd(opcode))); in EmulateCPRT() [all …]
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/openbmc/qemu/target/ppc/translate/ |
H A D | spe-impl.c.inc | 21 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], 22 cpu_gprh[rA(ctx->opcode)]); 28 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 29 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); 45 if (Rc(ctx->opcode)) \ 65 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 66 cpu_gpr[rB(ctx->opcode)]); \ 67 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ 68 cpu_gprh[rB(ctx->opcode)]); \ 91 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ [all …]
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/openbmc/linux/include/trace/events/ |
H A D | spmi.h | 16 TP_PROTO(u8 opcode, u8 sid, u16 addr, u8 len, const u8 *buf), 17 TP_ARGS(opcode, sid, addr, len, buf), 20 __field ( u8, opcode ) 28 __entry->opcode = opcode; 36 (int)__entry->opcode, (int)__entry->sid, 42 TP_PROTO(u8 opcode, u8 sid, u16 addr, int ret), 43 TP_ARGS(opcode, sid, addr, ret), 46 __field ( u8, opcode ) 53 __entry->opcode = opcode; 60 (int)__entry->opcode, (int)__entry->sid, [all …]
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/openbmc/qemu/target/hexagon/ |
H A D | iclass.c | 32 SlotMask find_iclass_slots(Opcode opcode, int itype) in find_iclass_slots() argument 35 if (GET_ATTRIB(opcode, A_ICOP)) { in find_iclass_slots() 37 } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT0ONLY)) { in find_iclass_slots() 39 } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT1ONLY)) { in find_iclass_slots() 41 } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT2ONLY)) { in find_iclass_slots() 43 } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT3ONLY)) { in find_iclass_slots() 45 } else if (GET_ATTRIB(opcode, A_COF) && in find_iclass_slots() 46 GET_ATTRIB(opcode, A_INDIRECT) && in find_iclass_slots() 47 !GET_ATTRIB(opcode, A_MEMLIKE) && in find_iclass_slots() 48 !GET_ATTRIB(opcode, A_MEMLIKE_PACKET_RULES)) { in find_iclass_slots() [all …]
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/openbmc/linux/arch/powerpc/xmon/ |
H A D | ppc.h | 1 /* ppc.h -- Header file for PowerPC opcode table 30 /* The opcode table is an array of struct powerpc_opcode. */ 34 /* The opcode name. */ 37 /* The opcode itself. Those bits which will be filled in with 39 unsigned long opcode; member 41 /* The opcode mask. This is used by the disassembler. This is a 43 opcode field, and zeroes indicating those bits which need not 47 /* One bit flags for the opcode. These are used to indicate which 52 /* One bit flags for the opcode. These are used to indicate which 63 /* The table itself is sorted by major opcode number, and is otherwise [all …]
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H A D | ppc-dis.c | 77 /* Find a match for INSN in the opcode table, given machine DIALECT. 78 A DIALECT of -1 is special, matching all machine opcode variations. */ 83 const struct powerpc_opcode *opcode; in lookup_powerpc() local 87 /* Find the first match in the opcode table for this major opcode. */ in lookup_powerpc() 88 for (opcode = powerpc_opcodes; opcode < opcode_end; ++opcode) in lookup_powerpc() 94 if ((insn & opcode->mask) != opcode->opcode in lookup_powerpc() 96 && ((opcode->flags & dialect) == 0 in lookup_powerpc() 97 || (opcode->deprecated & dialect) != 0))) in lookup_powerpc() 102 for (opindex = opcode->operands; *opindex != 0; opindex++) in lookup_powerpc() 111 return opcode; in lookup_powerpc() [all …]
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/openbmc/u-boot/post/lib_powerpc/ |
H A D | cpu_asm.h | 112 #define ASM_0(opcode) (opcode) argument 113 #define ASM_1(opcode, rd) ((opcode) + \ argument 115 #define ASM_1C(opcode, cr) ((opcode) + \ argument 117 #define ASM_11(opcode, rd, rs) ((opcode) + \ argument 120 #define ASM_11C(opcode, cd, cs) ((opcode) + \ argument 123 #define ASM_11X(opcode, rd, rs) ((opcode) + \ argument 126 #define ASM_11I(opcode, rd, rs, simm) ((opcode) + \ argument 130 #define ASM_11IF(opcode, rd, rs, simm) ((opcode) + \ argument 134 #define ASM_11S(opcode, rd, rs, sh) ((opcode) + \ argument 138 #define ASM_11IX(opcode, rd, rs, imm) ((opcode) + \ argument [all …]
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/openbmc/linux/tools/perf/scripts/python/ |
H A D | powerpc-hcalls.py | 20 # opcode: { 31 # opcode: nsec 153 def hcall_table_lookup(opcode): argument 154 if (opcode in hcall_table): 155 return hcall_table[opcode] 157 return opcode 164 for opcode in output: 165 h_name = hcall_table_lookup(opcode) 166 time = output[opcode]['time'] 167 cnt = output[opcode]['cnt'] [all …]
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/openbmc/linux/include/linux/pds/ |
H A D | pds_adminq.h | 146 * @opcode: opcode PDS_AQ_CMD_CLIENT_REG 154 u8 opcode; member 180 * @opcode: opcode PDS_AQ_CMD_CLIENT_UNREG 188 u8 opcode; member 195 * @opcode: opcode PDS_AQ_CMD_CLIENT_CMD 204 u8 opcode; member 310 * @opcode: Opcode PDS_AQ_CMD_LIF_IDENTIFY 321 u8 opcode; member 347 * @opcode: Opcode PDS_AQ_CMD_LIF_INIT 354 u8 opcode; member [all …]
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/openbmc/qemu/target/hexagon/mmvec/ |
H A D | decode_ext_mmvec.c | 34 uint16_t use_opcode = pkt->insn[i].opcode; in check_new_value() 49 if (!GET_ATTRIB(pkt->insn[j].opcode, A_CVI)) { in check_new_value() 66 def_opcode = pkt->insn[def_idx].opcode; in check_new_value() 103 if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) { in decode_mmvec_move_cvi_to_end() 105 uint16_t last_opcode = pkt->insn[last_inst].opcode; in decode_mmvec_move_cvi_to_end() 132 uint16_t opcode = pkt->insn[i].opcode; in decode_shuffle_for_execution_vops() local 133 if ((GET_ATTRIB(opcode, A_LOAD) && in decode_shuffle_for_execution_vops() 134 GET_ATTRIB(opcode, A_CVI_NEW)) || in decode_shuffle_for_execution_vops() 135 GET_ATTRIB(opcode, A_CVI_TMP)) { in decode_shuffle_for_execution_vops() 147 uint16_t opcode = pkt->insn[i].opcode; in decode_shuffle_for_execution_vops() local [all …]
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/openbmc/qemu/target/mips/tcg/ |
H A D | mxu_translate.c | 193 * The opcode organization of MXU instructions 197 * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning of 679 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32i2m() 680 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32i2m() 700 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32m2i() 701 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32m2i() 726 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s8ldd() 727 s8 = extract32(ctx->opcode, 10, 8); in gen_mxu_s8ldd() 728 optn3 = extract32(ctx->opcode, 18, 3); in gen_mxu_s8ldd() 729 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s8ldd() [all …]
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H A D | micromips_translate.c.inc | 18 * Table 6.2 microMIPS32 Encoding of Major Opcode Field 148 /* POOL32A encoding of minor opcode field */ 201 /* POOL32AXF encoding of minor opcode field extension */ 207 * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field 213 * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field 321 /* POOL32B encoding of minor opcode field (bits 15..12) */ 337 /* POOL32C encoding of minor opcode field (bits 15..12) */ 358 /* POOL32C LD-EVA encoding of minor opcode field (bits 11..9) */ 371 /* POOL32C ST-EVA encoding of minor opcode field (bits 11..9) */ 384 /* POOL32F encoding of minor opcode field (bits 5..0) */ [all …]
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H A D | nanomips_translate.c.inc | 1230 int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode)); 1231 int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); 1233 switch (extract32(ctx->opcode, 2, 2)) { 1251 int rt = extract32(ctx->opcode, 21, 5); 1252 int rs = extract32(ctx->opcode, 16, 5); 1253 int rd = extract32(ctx->opcode, 11, 5); 1255 switch (extract32(ctx->opcode, 3, 7)) { 1257 switch (extract32(ctx->opcode, 10, 1)) { 1270 gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); 1305 switch (extract32(ctx->opcode, 10, 1)) { [all …]
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/openbmc/linux/arch/riscv/include/asm/ |
H A D | insn-def.h | 25 .macro insn_r, opcode, func3, func7, rd, rs1, rs2 26 .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2 29 .macro insn_i, opcode, func3, rd, rs1, simm12 30 .insn i \opcode, \func3, \rd, \rs1, \simm12 37 .macro insn_r, opcode, func3, func7, rd, rs1, rs2 38 .4byte ((\opcode << INSN_R_OPCODE_SHIFT) | \ 46 .macro insn_i, opcode, func3, rd, rs1, simm12 47 .4byte ((\opcode << INSN_I_OPCODE_SHIFT) | \ 63 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \ argument 64 ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" [all …]
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/openbmc/linux/arch/powerpc/include/asm/ |
H A D | trace.h | 79 TP_PROTO(unsigned long opcode, unsigned long *args), 81 TP_ARGS(opcode, args), 86 __field(unsigned long, opcode) 90 __entry->opcode = opcode; 93 TP_printk("opcode=%lu", __entry->opcode), 100 TP_PROTO(unsigned long opcode, long retval, unsigned long *retbuf), 102 TP_ARGS(opcode, retval, retbuf), 107 __field(unsigned long, opcode) 112 __entry->opcode = opcode; 116 TP_printk("opcode=%lu retval=%ld", __entry->opcode, __entry->retval), [all …]
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/openbmc/linux/arch/x86/tools/ |
H A D | gen-insn-attr-x86.awk | 6 # Usage: awk -f gen-insn-attr-x86.awk x86-opcode-map.txt > inat-tables.c 37 print "/* x86 opcode map generated from x86-opcode-map.txt */" 130 # escape opcode table 141 # AVX/escape opcode table 145 if (tname == "") # AVX only opcode table 148 if (aid == -1 && eid == -1) # primary opcode table 268 # check if escaped opcode 287 opcode = $(i++) 292 # parse one opcode 305 # check if group opcode [all …]
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