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/openbmc/linux/arch/arm64/boot/dts/nuvoton/
H A Dnuvoton-common-npcm8xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16 compatible = "simple-bus";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dnuvoton,npcm750-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Reset controller
10 - Tomer Maimon <tmaimon77@gmail.com>
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
24 '#clock-cells':
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/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-common-npcm7xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&gic>;
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <25000000>;
[all …]
H A Dnuvoton-npcm750-runbmc-olympus.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
6 #include "nuvoton-npcm750.dtsi"
7 #include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi"
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Nuvoton npcm750 RunBMC Olympus";
14 compatible = "nuvoton,npcm750";
43 stdout-path = &serial3;
50 iio-hwmon {
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H A Dnuvoton-npcm730-gbs.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
10 compatible = "quanta,gbs-bmc","nuvoton,npcm730";
71 stdout-path = &serial0;
78 gpio-keys {
79 compatible = "gpio-keys";
80 sas-cable0 {
81 label = "sas-cable0";
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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dnuvoton,npcm750-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nuvoton,npcm750-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
13 The NPCM7XX ADC is a 10-bit converter and NPCM8XX ADC is a 12-bit converter,
19 - nuvoton,npcm750-adc
20 - nuvoton,npcm845-adc
36 vref-supply:
39 "#io-channel-cells":
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/openbmc/qemu/docs/system/arm/
H A Dnuvoton.rst1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
6 servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an
8 Hyperscale applications. The former is a superset of the latter, so NPCM750 has
11 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
13 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
16 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
18 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
21 - ``quanta-gbs-bmc`` Quanta GBS server BMC
22 - ``quanta-gsj`` Quanta GSJ server BMC
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dnuvoton,npcm-ece.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nuvoton,npcm-ece.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joseph Liu <kwliu@nuvoton.com>
11 - Marvin Lin <kflin@nuvoton.com>
19 - nuvoton,npcm750-ece
20 - nuvoton,npcm845-ece
29 - compatible
30 - reg
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H A Dnuvoton,npcm-vcd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nuvoton,npcm-vcd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joseph Liu <kwliu@nuvoton.com>
11 - Marvin Lin <kflin@nuvoton.com>
19 - nuvoton,npcm750-vcd
20 - nuvoton,npcm845-vcd
43 memory-region:
49 - compatible
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dnuvoton,npcm-pspi.txt6 - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX.
7 "nuvoton,npcm845-pspi" for Arbel NPCM8XX.
8 - #address-cells : should be 1. see spi-bus.txt
9 - #size-cells : should be 0. see spi-bus.txt
10 - specifies physical base address and size of the register.
11 - interrupts : contain PSPI interrupt.
12 - clocks : phandle of PSPI reference clock.
13 - clock-names: Should be "clk_apb5".
14 - pinctrl-names : a pinctrl state named "default" must be defined.
15 - pinctrl-0 : phandle referencing pin configuration of the device.
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/openbmc/linux/drivers/reset/
H A Dreset-npcm.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset-controller.h>
20 #include <soc/nuvoton/clock-npcm8xx.h>
40 /* NPCM7xx Reset registers */
109 writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR); in npcm_rc_restart()
126 spin_lock_irqsave(&rc->lock, flags); in npcm_rc_setclear_reset()
127 stat = readl(rc->base + ctrl_offset); in npcm_rc_setclear_reset()
129 writel(stat | rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
131 writel(stat & ~rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
132 spin_unlock_irqrestore(&rc->lock, flags); in npcm_rc_setclear_reset()
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
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H A Dgeneric-ehci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ehci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 - $ref: usb-hcd.yaml
14 - if:
19 const: ibm,usb-ehci-440epx
28 - items:
29 - enum:
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/openbmc/linux/drivers/usb/chipidea/
H A Dci_hdrc_npcm.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/reset-controller.h>
23 struct device *dev = ci->dev->parent; in npcm_udc_notify_event()
43 struct device *dev = &pdev->dev; in npcm_udc_probe()
45 ci = devm_kzalloc(&pdev->dev, sizeof(*ci), GFP_KERNEL); in npcm_udc_probe()
47 return -ENOMEM; in npcm_udc_probe()
50 ci->core_clk = devm_clk_get_optional(dev, NULL); in npcm_udc_probe()
51 if (IS_ERR(ci->core_clk)) in npcm_udc_probe()
52 return PTR_ERR(ci->core_clk); in npcm_udc_probe()
54 ret = clk_prepare_enable(ci->core_clk); in npcm_udc_probe()
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/openbmc/linux/drivers/watchdog/
H A Dnpcm_wdt.c1 // SPDX-License-Identifier: GPL-2.0
23 #define NPCM_WTRF BIT(2) /* Reset flag */
24 #define NPCM_WTRE BIT(1) /* Reset enable */
25 #define NPCM_WTR BIT(0) /* Reset counter */
60 val = readl(wdt->reg); in npcm_wdt_ping()
61 writel(val | NPCM_WTR, wdt->reg); in npcm_wdt_ping()
71 if (wdt->clk) in npcm_wdt_start()
72 clk_prepare_enable(wdt->clk); in npcm_wdt_start()
74 if (wdd->timeout < 2) in npcm_wdt_start()
76 else if (wdd->timeout < 3) in npcm_wdt_start()
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dnpcm_adc.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/reset.h>
35 struct reset_control *reset; member
106 regtemp = ioread32(info->regs + NPCM_ADCCON); in npcm_adc_isr()
108 iowrite32(regtemp, info->regs + NPCM_ADCCON); in npcm_adc_isr()
109 wake_up_interruptible(&info->wq); in npcm_adc_isr()
110 info->int_status = true; in npcm_adc_isr()
122 regtemp = ioread32(info->regs + NPCM_ADCCON); in npcm_adc_read()
124 info->int_status = false; in npcm_adc_read()
126 NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON); in npcm_adc_read()
[all …]
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_pwm-test.c204 ptrdiff_t diff = module - pwm_module_list; in pwm_module_index()
214 ptrdiff_t diff = pwm - pwm_list; in pwm_index()
229 response = qtest_qmp(qts, "{ 'execute': 'qom-get'," in pwm_qom_get()
271 response = qtest_qmp(qts, "{ 'execute': 'qom-set'," in mft_qom_set()
357 duty = MAX_DUTY - duty; in pwm_compute_duty()
365 return qtest_readl(qts, td->module->base_addr + offset); in pwm_read()
371 qtest_writel(qts, td->module->base_addr + offset, value); in pwm_write()
398 return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8); in pwm_read_ppr()
403 pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]); in pwm_write_ppr()
408 return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3); in pwm_read_csr()
[all …]
H A Dnpcm_gmac-test.c24 #define TYPE_NPCM_GMAC "npcm-gmac"
54 ptrdiff_t diff = mod - gmac_module_list; in gmac_module_index()
61 /* 32-bit register indices. Taken from npcm_gmac.c */
174 return qtest_readl(qts, mod->base_addr + regno); in gmac_read()
177 /* Check that GMAC registers are reset to default value */
181 const GMACModule *mod = td->module; in test_init()
182 QTestState *qts = qtest_init("-machine npcm750-evb"); in test_init()
245 "npcm7xx_gmac/gmac[%d]/%s", gmac_module_index(td->module), name); in gmac_add_test()
258 td->module = &gmac_module_list[i]; in main()
H A Dnpcm7xx_rng-test.c21 #include "libqtest-single.h"
64 /* Reset RNG and then enable it. */
77 while (retries-- > 0) { in rng_wait_ready()
87 * Perform a frequency (monobit) test, as defined by NIST SP 800-22, on the
88 * sequence in buf and return the P-value. This represents the probability of a
104 * Each 1 counts as 1, each 0 counts as -1. in calc_monobit_p()
105 * s = cp - (8 - cp) = 2 * cp - 8 in calc_monobit_p()
107 sn += 2 * ctpop8(buf[i]) - 8; in calc_monobit_p()
116 * Perform a runs test, as defined by NIST SP 800-22, and return the P-value.
136 for (k = 0; k < nr_bits - 1; k++) { in calc_runs_p()
[all …]
H A Dnpcm7xx_timer-test.c19 #include "libqtest-single.h"
37 /* Power-on default; used to re-initialize timers before each test. */
101 ptrdiff_t diff = tim - timer_block; in tim_index()
111 ptrdiff_t diff = t - timer; in timer_index()
121 return td->tim->irq_base + timer_index(td->timer); in tim_timer_irq()
129 writel(td->tim->base_addr + offset, value); in tim_write()
134 return readl(td->tim->base_addr + offset); in tim_read()
139 tim_write(td, td->timer->tcsr_offset, value); in tim_write_tcsr()
144 return tim_read(td, td->timer->tcsr_offset); in tim_read_tcsr()
149 tim_write(td, td->timer->ticr_offset, value); in tim_write_ticr()
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-npcm-pspi.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset.h>
22 struct reset_control *reset; member
37 #define DRIVER_NAME "npcm-pspi"
70 val = ioread16(priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_enable()
72 iowrite16(val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_enable()
79 val = ioread16(priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_disable()
81 iowrite16(val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_disable()
88 val = ioread16(priv->base + NPCM_PSPI_CTL1); in npcm_pspi_enable()
90 iowrite16(val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_enable()
[all …]
/openbmc/linux/drivers/peci/controller/
H A Dpeci-npcm.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset.h>
31 /* NPCM_PECI_CTL_STS - 0x00 : Control Register */
38 /* NPCM_PECI_RD_LENGTH - 0x04 : Command Register */
41 /* NPCM_PECI_CMD - 0x10 : Command Register */
44 /* NPCM_PECI_WR_LENGTH - 0x1C : Command Register */
47 /* NPCM_PECI_PDDR - 0x2C : Command Register */
75 struct npcm_peci *priv = dev_get_drvdata(controller->dev.parent); in npcm_peci_xfer()
76 unsigned long timeout = msecs_to_jiffies(priv->cmd_timeout_ms); in npcm_peci_xfer()
82 ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts, in npcm_peci_xfer()
[all …]
/openbmc/qemu/hw/arm/
H A Dnpcm7xx.c21 #include "hw/char/serial-mm.h"
24 #include "hw/qdev-clock.h"
25 #include "hw/qdev-properties.h"
30 #include "target/arm/cpu-qom.h"
79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
153 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
171 /* Direct memory-mapped access to SPI0 CS0-1. */
177 /* Direct memory-mapped access to SPI3 CS0-3. */
203 /* Direct memory-mapped access to each SMBus Module. */
328 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup), in npcm7xx_write_board_setup()
[all …]
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_of.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/reset.h>
36 struct device_node *np = ofdev->dev.of_node; in of_platform_serial_setup()
37 struct uart_port *port = &up->port; in of_platform_serial_setup()
43 pm_runtime_enable(&ofdev->dev); in of_platform_serial_setup()
44 pm_runtime_get_sync(&ofdev->dev); in of_platform_serial_setup()
46 if (of_property_read_u32(np, "clock-frequency", &clk)) { in of_platform_serial_setup()
49 info->clk = devm_clk_get(&ofdev->dev, NULL); in of_platform_serial_setup()
50 if (IS_ERR(info->clk)) { in of_platform_serial_setup()
51 ret = PTR_ERR(info->clk); in of_platform_serial_setup()
[all …]
/openbmc/linux/drivers/hwmon/
H A Dnpcm750-pwm-fan.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
7 #include <linux/hwmon-sysfs.h>
150 * 320RPM/pulse 2, ...-- 10.6Hz)
154 #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
155 #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
225 mutex_lock(&data->pwm_lock[module]); in npcm7xx_pwm_config_set()
228 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch)); in npcm7xx_pwm_config_set()
229 tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module)); in npcm7xx_pwm_config_set()
249 mutex_unlock(&data->pwm_lock[module]); in npcm7xx_pwm_config_set()
[all …]

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