| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Control/Host/ |
| H A D | NMI.interface.yaml | 2 It is a non-maskable interrupt or signal for triggering dumps from the host
6 - name: NMI
8 Generic method to initiate non maskable interrupt on all host
11 - xyz.openbmc_project.Common.Error.InternalFailure
|
| /openbmc/openbmc-test-automation/openpower/ |
| H A D | test_nmi_interface.robot | 2 Documentation Test Non-maskable interrupt functionality.
54 # secure_boot_mode Secure boot -> Enable-1 or Disable-0.
61 # Delete any pre-existing dump files.
62 OS Execute Command rm -rf /var/crash/*
66 ... '${os_release_info['id']}' == 'ubuntu' kdump-config show kdumpctl start
71 [Documentation] Inject non-maskable interrupt Redfish URI.
91 ... OS Execute Command ls -ltr /var/crash/* print_out=1
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Chassis/Buttons/ |
| H A D | NMI.interface.yaml | 3 is a non-maskable interrupt or signal for generating diagnostic traces and
8 - name: simPress
12 - xyz.openbmc_project.Chassis.Common.Error.UnsupportedCommand
13 - xyz.openbmc_project.Chassis.Common.Error.IOError
16 - name: Enabled
23 - xyz.openbmc_project.Chassis.Common.Error.UnsupportedCommand
24 - xyz.openbmc_project.Chassis.Common.Error.IOError
27 - name: Released
30 - name: Pressed
|
| /openbmc/qemu/hw/audio/ |
| H A D | gusemu_hal.c | 2 * GUSEMU32 - bus interface part
4 * Copyright (C) 2000-2007 Tibor "TS" Schütz
43 gusptr = state->gusdatapos; in gus_read()
76 /* case 1-5: */ /* general purpose emulation regs */ in gus_read()
90 /* case 0x20D: */ /* SB2xD is write only -> 2xE writes to it*/ in gus_read()
95 GUS_irqrequest(state, state->gusirq, 1); in gus_read()
119 if (state->gusdma >= 4) in gus_read()
126 GUS_irqclear(state, state->gusirq); in gus_read()
135 /* 48h: samp freq - write only */ in gus_read()
165 /* (pseudo IRQ-FIFO is processed during a gus_write(0x3X3,0x8f)) */ in gus_read()
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | exception.c | 4 * Copyright (c) 2004-2005 Jocelyn Mayer
25 #include "exec/helper-proto.h"
26 #include "exec/translation-block.h"
33 isa_mode = !!(env->hflags & MIPS_HFLAG_M16); in exception_resume_pc()
34 bad_pc = env->active_tc.PC | isa_mode; in exception_resume_pc()
35 if (env->hflags & MIPS_HFLAG_BMASK) { in exception_resume_pc()
40 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); in exception_resume_pc()
71 cs->halted = 1; in helper_wait()
75 * - no need to recover PC and icount. in helper_wait()
85 env->active_tc.PC = tb->pc; in mips_cpu_synchronize_from_tb()
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|
| /openbmc/qemu/target/rx/ |
| H A D | helper.c | 23 #include "accel/tcg/cpu-ldst.h"
28 if (env->psw_pm == 0) { in rx_cpu_unpack_psw()
29 env->psw_ipl = FIELD_EX32(psw, PSW, IPL); in rx_cpu_unpack_psw()
32 env->psw_pm = FIELD_EX32(psw, PSW, PM); in rx_cpu_unpack_psw()
34 env->psw_u = FIELD_EX32(psw, PSW, U); in rx_cpu_unpack_psw()
35 env->psw_i = FIELD_EX32(psw, PSW, I); in rx_cpu_unpack_psw()
37 env->psw_o = FIELD_EX32(psw, PSW, O) << 31; in rx_cpu_unpack_psw()
38 env->psw_s = FIELD_EX32(psw, PSW, S) << 31; in rx_cpu_unpack_psw()
39 env->psw_z = 1 - FIELD_EX32(psw, PSW, Z); in rx_cpu_unpack_psw()
40 env->psw_c = FIELD_EX32(psw, PSW, C); in rx_cpu_unpack_psw()
[all …]
|
| /openbmc/qemu/docs/system/arm/ |
| H A D | emulation.rst | 3 A-profile CPU architecture support
7 Armv8 and Armv9 versions of the A-profile architecture. It also has support for
10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
11 - FEAT_AA32EL0 (Support for AArch32 at EL0)
12 - FEAT_AA32EL1 (Support for AArch32 at EL1)
13 - FEAT_AA32EL2 (Support for AArch32 at EL2)
14 - FEAT_AA32EL3 (Support for AArch32 at EL3)
15 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
16 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
17 - FEAT_AA64EL0 (Support for AArch64 at EL0)
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|
| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/ |
| H A D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 1999-2007 Tensilica Inc.
23 /*----------------------------------------------------------------------
25 ----------------------------------------------------------------------*/
27 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
33 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
34 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
44 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
66 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
73 /*----------------------------------------------------------------------
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|
| /openbmc/qemu/target/xtensa/core-dc232b/ |
| H A D | core-isa.h | 8 * Copyright (c) 1999-2007 Tensilica Inc.
24 /*----------------------------------------------------------------------
26 ----------------------------------------------------------------------*/
28 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
34 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
45 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
67 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
74 /*----------------------------------------------------------------------
76 ----------------------------------------------------------------------*/
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|
| /openbmc/qemu/hw/m68k/ |
| H A D | q800-glue.c | 25 #include "hw/m68k/q800-glue.h"
29 #include "hw/qdev-properties.h"
65 * Level 7: Non-maskable: parity errors, RESET button
76 if (s->auxmode) { in GLUE_set_irq()
89 qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level); in GLUE_set_irq()
101 /* Route to VIA2 instead, negative edge-triggered */ in GLUE_set_irq()
102 qemu_set_irq(s->irqs[GLUE_IRQ_ASC], !level); in GLUE_set_irq()
141 s->ipr |= 1 << irq; in GLUE_set_irq()
143 s->ipr &= ~(1 << irq); in GLUE_set_irq()
146 for (i = 7; i >= 0; i--) { in GLUE_set_irq()
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|
| /openbmc/qemu/target/xtensa/core-dc233c/ |
| H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2010 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
65 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
90 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
111 /*----------------------------------------------------------------------
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|
| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/ |
| H A D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 1999-2010 Tensilica Inc.
23 /*----------------------------------------------------------------------
25 ----------------------------------------------------------------------*/
27 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
33 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
34 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
44 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
69 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
90 /*----------------------------------------------------------------------
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|
| /openbmc/qemu/target/xtensa/core-lx106/ |
| H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2010 Tensilica Inc.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
66 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
91 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
102 /*----------------------------------------------------------------------
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|
| /openbmc/qemu/target/xtensa/core-test_kc705_be/ |
| H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
88 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
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|
| /openbmc/u-boot/arch/xtensa/include/asm/arch-de212/ |
| H A D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 1999-2015 Tensilica Inc.
23 /*----------------------------------------------------------------------
25 ----------------------------------------------------------------------*/
27 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
33 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
34 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
35 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
46 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
67 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
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|
| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
89 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
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|
| /openbmc/qemu/target/xtensa/core-sample_controller/ |
| H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2016 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
89 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
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|
| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3.c | 33 if (prio != cs->hppi.prio) { in irqbetter()
34 return prio < cs->hppi.prio; in irqbetter()
38 * The same priority IRQ with non-maskable property should signal to in irqbetter()
41 if (nmi != cs->hppi.nmi) { in irqbetter()
49 if (irq <= cs->hppi.irq) { in irqbetter()
59 * of 32), and return a 32-bit integer which has a bit set for each in gicd_int_pending()
67 * Conveniently we can bulk-calculate this with bitwise operations. in gicd_int_pending()
70 uint32_t pending = *gic_bmp_ptr32(s->pending, irq); in gicd_int_pending()
71 uint32_t edge_trigger = *gic_bmp_ptr32(s->edge_trigger, irq); in gicd_int_pending()
72 uint32_t level = *gic_bmp_ptr32(s->level, irq); in gicd_int_pending()
[all …]
|
| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2020 Tensilica Inc.
34 //depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko)
46 /*----------------------------------------------------------------------
48 ----------------------------------------------------------------------*/
50 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
56 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
57 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
58 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
69 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
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|
| /openbmc/qemu/target/xtensa/core-fsf/ |
| H A D | core-isa.h | 8 * Copyright (C) 1999-2006 Tensilica Inc.
24 /*----------------------------------------------------------------------
26 ----------------------------------------------------------------------*/
28 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
34 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
44 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
66 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
73 /*----------------------------------------------------------------------
75 ----------------------------------------------------------------------*/
[all …]
|
| /openbmc/qemu/target/xtensa/core-dsp3400/ |
| H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2010 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
65 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
90 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
109 /*----------------------------------------------------------------------
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|
| /openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/ |
| H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2019 Tensilica Inc.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
88 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
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|
| /openbmc/qemu/target/sparc/ |
| H A D | cpu.h | 5 #include "cpu-qom.h"
6 #include "exec/cpu-common.h"
7 #include "exec/cpu-defs.h"
8 #include "exec/cpu-interrupt.h"
9 #include "qemu/cpu-float.h"
245 #include "cpu-feature.h.inc"
252 #include "cpu-feature.h.inc"
418 * Z is represented as == 0; any non-zero value is !Z.
419 * For sparc64, the high 32-bits of icc.Z are garbage.
446 * Single-element FPU fault queue, with address and insn,
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|
| /openbmc/qemu/docs/ |
| H A D | pcie.txt | 25 QEMU does not have a clear socket-device matching mechanism
43 Note: Integrated Endpoints are not hot-pluggable.
51 (2) PCI Express Root Ports (pcie-root-port), for starting exclusively
54 (3) PCI Express to PCI Bridge (pcie-pci-bridge), for starting legacy PCI
57 (4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses
61 ----------------------------------------------------------------------------
63 ----------- ------------------ ------------------- --------------
64 | PCI Dev | | PCIe Root Port | | PCIe-PCI Bridge | | pxb-pcie |
65 ----------- ------------------ ------------------- --------------
68 -device <dev>[,bus=pcie.0]
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|
| /openbmc/qemu/qapi/ |
| H A D | run-state.json | 1 # -*- Mode: Python -*-
18 # @finish-migrate: guest is paused to finish the migration process
22 # the end of the migration. This depends on the command-line -S
26 # @internal-error: An internal error that prevents further guest
29 # @io-error: the last IOP has failed and the device is configured to
36 # @prelaunch: QEMU was started with -S and guest has not started
38 # @restore-vm: guest is paused to restore VM state
42 # @save-vm: guest is paused to save the VM state
44 # @shutdown: guest is shut down (and -no-shutdown is in use)
51 # @guest-panicked: guest has been panicked as a result of guest OS
[all …]
|