| /openbmc/linux/tools/testing/selftests/bpf/prog_tests/ |
| H A D | btf_endian.c | 1 // SPDX-License-Identifier: GPL-2.0
11 enum btf_endianness endian = BTF_LITTLE_ENDIAN; in test_btf_endian() local
13 enum btf_endianness endian = BTF_BIG_ENDIAN; in test_btf_endian()
17 enum btf_endianness swap_endian = 1 - endian; in test_btf_endian()
25 /* Load BTF in native endianness */ in test_btf_endian()
30 ASSERT_EQ(btf__endianness(btf), endian, "endian"); in test_btf_endian()
32 ASSERT_EQ(btf__endianness(btf), swap_endian, "endian"); in test_btf_endian()
34 /* Get raw BTF data in non-native endianness... */ in test_btf_endian()
44 ASSERT_EQ(btf__endianness(swap_btf), swap_endian, "endian"); in test_btf_endian()
51 /* both raw data should be identical (with non-native endianness) */ in test_btf_endian()
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| /openbmc/linux/Documentation/devicetree/bindings/ |
| H A D | common-properties.txt | 5 ----------
13 - big-endian: Boolean; force big endian register accesses
15 know the peripheral always needs to be accessed in big endian (BE) mode.
16 - little-endian: Boolean; force little endian register accesses
18 peripheral always needs to be accessed in little endian (LE) mode.
19 - native-endian: Boolean; always use register accesses matched to the
20 endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
21 BE vmlinux -> ioread32be/iowrite32be). In this case no byte swaps
22 will ever be performed. Use this if the hardware "self-adjusts"
27 In such cases, little-endian is the preferred default, but it is not
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| /openbmc/linux/Documentation/devicetree/bindings/regmap/ |
| H A D | regmap.txt | 5 little-endian,
6 big-endian,
7 native-endian: See common-properties.txt for a definition
10 Regmap defaults to little-endian register access on MMIO based
12 architectures that typically run big-endian operating systems
13 (e.g. PowerPC), registers can be defined as big-endian and must
16 On SoCs that can be operated in both big-endian and little-endian
19 chips), "native-endian" is used to allow using the same device tree
23 Scenario 1 : a register set in big-endian mode.
27 big-endian;
|
| /openbmc/linux/arch/mips/boot/dts/brcm/ |
| H A D | bcm7346.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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| H A D | bcm7125.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <202500000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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| H A D | bcm7358.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
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| H A D | bcm7435.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
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| H A D | bcm7425.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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| H A D | bcm7360.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
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| H A D | bcm7362.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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|
| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | intel,ixp4xx-expansion-bus-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15 - Linus Walleij <linus.walleij@linaro.org>
19 pattern: '^bus@[0-9a-f]+$'
23 - enum:
24 - intel,ixp42x-expansion-bus-controller
25 - intel,ixp43x-expansion-bus-controller
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| /openbmc/qemu/include/qemu/ |
| H A D | bswap.h | 68 * Convert the value @v from the specified format to the native
79 * Convert the value @v from the native endianness of the host CPU to
90 * Do an in-place conversion of the value pointed to by @v from the
91 * specified format to the native endianness of the host CPU.
100 * Do an in-place conversion of the value pointed to by @v from the
101 * native endianness of the host CPU to the specified format.
114 #define CPU_CONVERT(endian, size, type)\ argument
115 static inline type endian ## size ## _to_cpu(type v)\
117 return glue(endian, _bswap)(v, size);\
120 static inline type cpu_to_ ## endian ## size(type v)\
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | bitops.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Big endian support: Copyright 2001, Nicolas Pitre
34 * First, the atomic bitops. These use native endian.
123 #include <asm-generic/bitops/non-atomic.h>
126 * A note about Endian-ness.
127 * -------------------------
129 * When the ARM is put into big endian mode via CR15, the processor
132 * ------------ physical data bus bits -----------
137 * This means that reading a 32-bit word at address 0 returns the same
138 * value irrespective of the endian mode bit.
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| /openbmc/openbmc/poky/meta/recipes-core/glibc/ |
| H A D | ldconfig-native_2.12.1.bb | 1 SUMMARY = "A standalone native ldconfig build"
3 LICENSE = "GPL-2.0-or-later"
7 SRC_URI = "file://ldconfig-native-2.12.1.tar.bz2 \
9 file://ldconfig_aux-cache_path_fix.patch \
11 file://endian-ness_handling.patch \
13 file://endianess-header.patch \
14 file://ldconfig-default-to-all-multilib-dirs.patch \
15 file://endian-ness_handling_fix.patch \
16 file://add-64-bit-flag-for-ELF64-entries.patch \
17 file://no-aux-cache.patch \
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| /openbmc/openbmc/poky/meta/recipes-core/glibc/ldconfig-native-2.12.1/ |
| H A D | endianess-header.patch | 1 Upstream-Status: Inappropriate [fix poky patch]
3 This patch fixes build issues with a previous endian-ness_handling.patch on
9 diff -purN ldconfig-native-2.12.1.orig/endian_extra.h ldconfig-native-2.12.1/endian_extra.h
10 --- ldconfig-native-2.12.1.orig/endian_extra.h 1969-12-31 18:00:00.000000000 -0600
11 +++ ldconfig-native-2.12.1/endian_extra.h 2011-07-19 18:09:14.323048417 -0500
12 @@ -0,0 +1,64 @@
29 + 02111-1307 USA. */
31 +#include <endian.h>
77 diff -purN ldconfig-native-2.12.1.orig/cache.c ldconfig-native-2.12.1/cache.c
78 --- ldconfig-native-2.12.1.orig/cache.c 2011-07-19 18:21:28.347041301 -0500
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-mmio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17 NAND-style parallel busses.
22 - brcm,bcm6345-gpio
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| /openbmc/linux/arch/xtensa/boot/dts/ |
| H A D | xtfpga.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 compatible = "cdns,xtensa-xtfpga";
4 #address-cells = <1>;
5 #size-cells = <1>;
6 interrupt-parent = <&pic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 compatible = "cdns,xtensa-cpu";
28 compatible = "cdns,xtensa-pic";
33 #interrupt-cells = <2>;
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| /openbmc/u-boot/arch/xtensa/dts/ |
| H A D | xtfpga.dtsi | 2 compatible = "cdns,xtensa-xtfpga";
3 #address-cells = <1>;
4 #size-cells = <1>;
5 interrupt-parent = <&pic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
20 compatible = "cdns,xtensa-cpu";
23 * clock-frequency = <100000000>;
29 compatible = "cdns,xtensa-pic";
34 #interrupt-cells = <2>;
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| /openbmc/qemu/crypto/ |
| H A D | block-luks-priv.h | 4 * Copyright (c) 2015-2016 Red Hat, Inc.
24 #include "block-luks.h"
38 * docs/on-disk-format.pdf
79 * This struct is written to disk in big-endian format,
80 * but operated upon in native-endian format.
91 /* number of anti-forensic stripes */
96 * This struct is written to disk in big-endian format,
97 * but operated upon in native-endian format.
109 /* cipher mode specification (cbc-plain, xts-essiv:sha256, etc) */
|
| /openbmc/openbmc/poky/meta/classes-recipe/ |
| H A D | siteinfo.bbclass | 4 # SPDX-License-Identifier: MIT
13 # where 'target' == "<arch>-<os>"
16 # * target: Returns the target name ("<arch>-<os>")
17 # * endianness: Return "be" for big endian targets, "le" for little endian
26 …"allarch": "endian-little bit-32", # bogus, but better than special-casing the checks below for al…
27 "aarch64": "endian-little bit-64 arm-common arm-64",
28 "aarch64_be": "endian-big bit-64 arm-common arm-64",
29 "arc": "endian-little bit-32 arc-common",
30 "arceb": "endian-big bit-32 arc-common",
31 "arm": "endian-little bit-32 arm-common arm-32",
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| /openbmc/linux/tools/testing/selftests/powerpc/tm/ |
| H A D | tm-trap.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 * to zero which determines a BE endianness that is the native
27 * endianness "flipped back" to the native endianness (BE).
67 thread_endianness = MSR_LE & ucp->uc_mcontext.gp_regs[PT_MSR]; in trap_signal_handler()
70 * Little-Endian Machine in trap_signal_handler()
95 * the return from the signal handler the endianness in- in trap_signal_handler()
98 * and (4) are executed (tbegin.; trap;) and we get sim- in trap_signal_handler()
109 * a trap caught in non-transactional mode is the very in trap_signal_handler()
116 ucp->uc_mcontext.gp_regs[PT_NIP] += 16; in trap_signal_handler()
123 ucp->uc_mcontext.gp_regs[PT_MSR] |= 1UL; in trap_signal_handler()
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| /openbmc/linux/arch/m68k/include/asm/ |
| H A D | io_no.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * The non-MMU m68k and ColdFire IO and memory mapped hardware access
13 * functions have always worked in CPU native endian. We need to define
14 * that behavior here first before we include asm-generic/io.h.
50 return (addr >= IOMEMBASE) && (addr <= IOMEMBASE + IOMEMSIZE - 1); in __cf_internalio()
59 * We need to treat built-in peripherals and bus based address ranges
60 * differently. Local built-in peripherals (and the ColdFire SoC parts
61 * have quite a lot of them) are always native endian - which is big
62 * endian on m68k/ColdFire. Bus based address ranges, like the PCI bus,
63 * are accessed little endian - so we need to byte swap those.
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| /openbmc/qemu/include/standard-headers/linux/ |
| H A D | virtio_pcidev.h | 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
8 #include "standard-headers/linux/types.h"
11 * enum virtio_pcidev_ops - virtual PCI device operations
14 * the @data field should be filled in by the device (in little endian).
16 * the @data field contains the data to write (in little endian).
18 * the @data field should be filled in by the device (in little endian).
20 * the @data field contains the data to write (in little endian).
23 * @VIRTIO_PCIDEV_OP_INT: legacy INTx# pin interrupt, the addr field is 1-4 for
25 * @VIRTIO_PCIDEV_OP_MSI: MSI(-X) interrupt, this message basically transports
26 * the 16- or 32-bit write that would otherwise be done into memory,
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| /openbmc/linux/include/uapi/linux/ |
| H A D | virtio_pcidev.h | 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
11 * enum virtio_pcidev_ops - virtual PCI device operations
14 * the @data field should be filled in by the device (in little endian).
16 * the @data field contains the data to write (in little endian).
18 * the @data field should be filled in by the device (in little endian).
20 * the @data field contains the data to write (in little endian).
23 * @VIRTIO_PCIDEV_OP_INT: legacy INTx# pin interrupt, the addr field is 1-4 for
25 * @VIRTIO_PCIDEV_OP_MSI: MSI(-X) interrupt, this message basically transports
26 * the 16- or 32-bit write that would otherwise be done into memory,
44 * struct virtio_pcidev_msg - virtio PCI device operation
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| /openbmc/linux/tools/objtool/include/objtool/ |
| H A D | endianness.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <endian.h>
11 * compilation for little endian on big endian and vice versa.
12 * To be used for multi-byte values conversion, which are read from / about
13 * to be written to a target native endianness ELF file.
18 (elf->ehdr.e_ident[EI_DATA] == ELFDATA2LSB); in need_bswap()
|