| /openbmc/linux/drivers/mtd/nand/ |
| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
10 #define pr_fmt(fmt) "nand: " fmt
13 #include <linux/mtd/nand.h>
16 * nanddev_isbad() - Check if a block is bad
17 * @nand: NAND device
22 bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) in nanddev_isbad() argument
27 if (nanddev_bbt_is_initialized(nand)) { in nanddev_isbad()
31 entry = nanddev_bbt_pos_to_entry(nand, pos); in nanddev_isbad()
32 status = nanddev_bbt_get_block_status(nand, entry); in nanddev_isbad()
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| H A D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
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| H A D | ecc-mxic.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Macronix external hardware ECC engine for NAND devices, also
4 * called DPE for Data Processing Engine.
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
53 /* ECC Chunk Size */
63 /* ECC Chunk Count */
98 /* ECC machinery */
124 static struct mxic_ecc_engine *nand_to_mxic(struct nand_device *nand) in nand_to_mxic() argument
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| H A D | ecc-sw-bch.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file provides ECC correction for more than 1 bit per block of data,
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
19 * @nand: NAND device
21 * @code: Output buffer with ECC
23 int nand_ecc_sw_bch_calculate(struct nand_device *nand, in nand_ecc_sw_bch_calculate() argument
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
29 memset(code, 0, engine_conf->code_size); in nand_ecc_sw_bch_calculate()
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| H A D | ecc-sw-hamming.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains an ECC algorithm that detects and corrects 1 bit
9 * Completely replaces the previous ECC implementation which was written by:
14 * can be found in Documentation/driver-api/mtd/nand_ecc.rst
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/nand-ecc-sw-hamming.h>
75 * addressbits is a lookup table to filter out the bits from the xor-ed
76 * ECC data that identify the faulty location.
294 * leaving it out gives slightly worse results. No idea why, probably in ecc_sw_hamming_calculate()
307 * Finally calculate the ECC bits. in ecc_sw_hamming_calculate()
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
16 This file covers the generic description of a NAND chip. It implies that the
17 bus interface should not be taken into account: both raw NAND devices and
18 SPI-NAND devices are concerned by this description.
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| /openbmc/u-boot/doc/ |
| H A D | README.nand | 1 # SPDX-License-Identifier: GPL-2.0+
2 NAND FLASH commands and notes
12 nand bad
15 nand device
16 Print information about the current NAND device.
18 nand device num
21 nand erase off|partition size
22 nand erase clean [off|partition size]
32 If `clean' is specified, a JFFS2-style clean marker is written to
40 nand info
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| /openbmc/linux/include/linux/mtd/ |
| H A D | nand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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| H A D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
87 * Constants for Hardware ECC
89 /* Reset Hardware ECC for read */
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | omap2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
21 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
131 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Raw/Parallel NAND Device Support"
8 NAND flash devices. For further information see
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
13 comment "Raw/parallel NAND flash controllers"
19 tristate "Denali NAND controller on Intel Moorestown"
23 Enable the driver for NAND flash on Intel Moorestown, using the
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
31 Enable the driver for NAND flash on platforms using a Denali NAND
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| H A D | pl35x-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ARM PL35X NAND flash controller driver
31 #define PL35X_NANDC_DRIVER_NAME "pl35x-nand-controller"
58 /* SMC ECC status register (RO) */
61 /* SMC ECC configuration register */
68 /* SMC ECC command 1 register */
74 /* SMC ECC command 2 register */
80 /* SMC ECC value registers (RO) */
86 /* NAND AXI interface */
126 * struct pl35x_nandc - NAND flash controller driver structure
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| H A D | socrates_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
33 * socrates_nand_write_buf - write buffer to chip
34 * @this: NAND chip object
45 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
52 * socrates_nand_read_buf - read chip data into buffer
53 * @this: NAND chip object
66 out_be32(host->io_base, val); in socrates_nand_read_buf()
68 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
74 * socrates_nand_read_byte - read one byte from the chip
85 * Hardware specific access to control-lines
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| H A D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
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| H A D | xway_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
15 /* nand registers */
19 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
20 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
25 * nand commands
26 * The pins of the NAND chip are selected based on the address bits of the
27 * "register" read and write. There are no special registers, but an
42 /* we need to tel the ebu which addr we mapped the nand to */
46 /* we need to tell the EBU that we have nand attached and set it up properly */
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| H A D | nand_base.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
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| H A D | r852.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
14 /* nand interface + ecc
15 byte write/read does one cycle on nand data lines.
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
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| H A D | arasan-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
150 * struct anand - Defines the NAND chip related information
151 * @node: Used to store NAND chips into a list
152 * @chip: NAND chip information structure
153 * @rb: Ready-busy line
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | omap_gpmc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
15 #include <nand.h>
54 * omap_nand_hwcontrol - Set the address pointers corretly for the
62 int cs = info->cs; in omap_nand_hwcontrol()
70 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; in omap_nand_hwcontrol()
73 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; in omap_nand_hwcontrol()
76 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; in omap_nand_hwcontrol()
81 writeb(cmd, this->IO_ADDR_W); in omap_nand_hwcontrol()
89 return gpmc_cfg->status & (1 << (8 + info->ws)); in omap_dev_ready()
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| H A D | tegra_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 #include <nand.h>
15 #include <asm/arch-tegra/clk_rst.h>
29 /* ECC bytes to be generated for tag data */
34 .compatible = "nvidia,tegra20-nand",
41 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
43 * Main area Ecc(36)
45 * Tag data Ecc(4)
87 /* Information about an attached NAND chip */
91 struct gpio_desc wp_gpio; /* write-protect GPIO */
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| H A D | mxs_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 NAND flash driver
9 * Freescale GPMI NFC NAND Flash Driver
24 #include <asm/arch/imx-regs.h>
25 #include <asm/mach-imx/regs-bch.h>
26 #include <asm/mach-imx/regs-gpmi.h>
56 uint32_t addr = (uint32_t)info->data_buf; in mxs_nand_flush_data_buf()
58 flush_dcache_range(addr, addr + info->data_buf_size); in mxs_nand_flush_data_buf()
63 uint32_t addr = (uint32_t)info->data_buf; in mxs_nand_inval_data_buf()
65 invalidate_dcache_range(addr, addr + info->data_buf_size); in mxs_nand_inval_data_buf()
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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| /openbmc/linux/drivers/mtd/nand/raw/ingenic/ |
| H A D | ingenic_ecc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx ECC common code
19 * ingenic_ecc_calculate() - calculate ECC for a data buffer
20 * @ecc: ECC device.
21 * @params: ECC parameters.
23 * @ecc_code: output buffer with ECC.
25 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
28 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
32 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
36 * ingenic_ecc_correct() - detect and correct bit errors
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| H A D | ingenic_nand_drv.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ47xx NAND driver
23 #include <linux/jz4780-nemc.h>
27 #define DRV_NAME "ingenic-nand"
44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
78 return -ERANGE; in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
81 oobregion->offset = 12; in qi_lb60_ooblayout_ecc()
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| /openbmc/linux/drivers/mtd/nand/spi/ |
| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Micron Technology, Inc.
10 #define pr_fmt(fmt) "spi-nand: " fmt
21 #include <linux/spi/spi-mem.h>
26 spinand->scratchbuf); in spinand_read_reg_op()
29 ret = spi_mem_exec_op(spinand->spimem, &op); in spinand_read_reg_op()
33 *val = *spinand->scratchbuf; in spinand_read_reg_op()
40 spinand->scratchbuf); in spinand_write_reg_op()
42 *spinand->scratchbuf = val; in spinand_write_reg_op()
43 return spi_mem_exec_op(spinand->spimem, &op); in spinand_write_reg_op()
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