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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
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H A Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raw NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
19 {size} bytes for a particular raw NAND chip.
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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/openbmc/u-boot/board/work-microwave/work_92105/
H A Dwork_92105.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
27 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); in reset_periph()
28 writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); in reset_periph()
30 writel(0, &wdt->mctrl); in reset_periph()
31 clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); in reset_periph()
38 /* enable I2C, SSP, MAC, NAND */ in board_early_init_f()
39 lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */ in board_early_init_f()
51 /* Set NAND !WP to 1 through GPO_19 */ in board_early_init_r()
65 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-db-dxbc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-DXBC2 board
7 * Based on armada-xp-db.dts
9 * Note: this Device Tree assumes that the bootloader has remapped the
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx4251.dtsi"
24 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
43 devbus,bus-width = <16>;
44 devbus,turn-off-ps = <60000>;
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H A Dkirkwood-pogoplug-series-4.dts1 // SPDX-License-Identifier: GPL-2.0
3 * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4
10 /dts-v1/;
13 #include "kirkwood-6192.dtsi"
14 #include <dt-bindings/input/linux-event-codes.h>
18 compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192",
27 stdout-path = "uart0:115200n8";
31 compatible = "gpio-keys";
32 #address-cells = <1>;
33 #size-cells = <0>;
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H A Darmada-370-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6710-BP-DDR3)
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * Note: this Device Tree assumes that the bootloader has remapped the
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include "armada-370.dtsi"
27 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
30 stdout-path = "serial0:115200n8";
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H A Darmada-370-rd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (RD-88F6710-A1)
6 * Copied from arch/arm/boot/dts/armada-370-db.dts
10 * Note: this Device Tree assumes that the bootloader has remapped the
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include <dt-bindings/input/input.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
23 #include <dt-bindings/leds/common.h>
24 #include <dt-bindings/gpio/gpio.h>
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H A Darmada-xp-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-78460-BP)
6 * Copyright (C) 2012-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * Note: this Device Tree assumes that the bootloader has remapped the
16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
23 /dts-v1/;
24 #include "armada-xp-mv78460.dtsi"
28 …compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx31-lite.dts1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
5 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "logicpd,imx31-lite", "fsl,imx31";
17 stdout-path = &uart1;
26 compatible = "gpio-leds";
43 nand-bus-width = <8>;
44 nand-ecc-mode = "hw";
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H A Dimx27-phytec-phycore-rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include "imx27-phytec-phycore-som.dtsi"
9 compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
12 stdout-path = &uart1;
16 model = "Sharp-LQ035Q7";
17 bits-per-pixel = <16>;
20 display-timings {
21 native-mode = <&timing0>;
23 clock-frequency = <5500000>;
26 hback-porch = <5>;
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H A Dimx53-tx53.dtsi2 * Copyright 2012-2017 <LW@KARO-electronics.de>
3 * based on imx53-qsb.dts
7 * This file is dual-licensed: you can use it either under the terms
46 #include <dt-bindings/gpio/gpio.h>
49 model = "Ka-Ro electronics TX53 module";
62 reg-can-xcvr = &reg_can_xcvr;
69 clock-frequency = <0>;
73 mclk: clock-mclk {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
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H A Dimx6q-arm2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 compatible = "fsl,imx6q-arm2", "fsl,imx6q";
20 reg_3p3v: regulator-3p3v {
21 compatible = "regulator-fixed";
22 regulator-name = "3P3V";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
25 regulator-always-on;
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H A Dimx6qdl-phytec-pfla02.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Phytec phyFLEX-i.MX6 Quad";
10 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
17 reg_usb_otg_vbus: regulator-usb-otg-vbus {
18 compatible = "regulator-fixed";
19 regulator-name = "usb_otg_vbus";
20 regulator-min-microvolt = <5000000>;
21 regulator-max-microvolt = <5000000>;
23 enable-active-high;
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/openbmc/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm4908-asus-gt-ac5300.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
10 compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca";
11 model = "Asus GT-AC5300";
18 gpio-keys-polled {
19 compatible = "gpio-keys-polled";
20 poll-interval = <100>;
22 key-wifi {
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/openbmc/linux/drivers/mtd/nand/raw/
H A Dnandsim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NAND flash simulator.
9 * Note: NS means "NAND Simulator".
132 MODULE_PARM_DESC(id_bytes, "The ID bytes returned by NAND Flash 'read ID' command");
133 MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufact…
134 MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID…
135 MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command (obsolete…
136 MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command (obsolet…
142 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
143 MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
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H A Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
14 /* nand interface + ecc
15 byte write/read does one cycle on nand data lines.
28 /* but has to be set on start...*/
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
33 #define R852_CTL_WRITE 0x80 /* set when performing writes (#WP) */
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
71 /* physical DMA address - 32 bit value*/
77 #define R852_DMA_MEMORY 0x01 /* (memory <-> internal hw buffer) */
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H A Dlpc32xx_slc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NXP LPC32XX NAND SLC driver
24 #include <linux/dma-mapping.h>
30 #define LPC32XX_MODNAME "lpc32xx-nand"
33 * SLC NAND controller register offsets
55 #define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */
72 #define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
73 #define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
74 #define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */
86 #define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
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H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
213 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_rs_ecc()
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/openbmc/linux/Documentation/driver-api/
H A Dmtdnand.rst2 MTD NAND Driver Programming Interface
10 The generic NAND driver supports almost all NAND and AG-AND based chips
15 board drivers or filesystem drivers suitable for NAND devices.
26 struct member has a short description which is marked with an [XXX]
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
45 These functions are exported and provide the interface to the NAND
48 - [GENERIC]
53 - [DEFAULT]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-pandora-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/input/input.h>
14 cpu0-supply = <&vcc>;
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <26000000>;
35 compatible = "connector-analog-tv";
40 remote-endpoint = <&venc_out>;
45 gpio-leds {
47 compatible = "gpio-leds";
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/openbmc/linux/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
17 #include <linux/dma-mapping.h>
36 * This flag controls if WP stays on between erase/write commands to mitigate
94 /* 512B flash cache in the NAND controller HW */
237 /* List of NAND hosts (one for each chip-select) */
240 /* EDU info, per-transaction */
261 /* in-memory cache of the FLASH_CACHE, used only for some commands */
267 const u8 *cs_offsets; /* within each chip-select */
278 /* for low-power standby/resume only */
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/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
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H A Dbcm-ns.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
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/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
5 /dts-v1/;
10 compatible = "fsl,imx28-evk", "fsl,imx28";
18 reg_3p3v: regulator-3p3v {
19 compatible = "regulator-fixed";
20 regulator-name = "3P3V";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
23 regulator-always-on;
26 reg_vddio_sd0: regulator-vddio-sd0 {
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/openbmc/u-boot/arch/arm/dts/
H A Dtegra20-harmony.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uartd;
38 display-timings {
40 /* Seaboard has 1366x768 */
41 clock-frequency = <42430000>;
44 hback-porch = <138>;
45 hfront-porch = <34>;
46 hsync-len = <136>;
47 vback-porch = <21>;
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