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/openbmc/linux/Documentation/devicetree/bindings/mux/
H A Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common multiplexer controller provider
10 - Peter Rosin <peda@axentia.se>
13 A multiplexer (or mux) controller will have one, or several, consumer devices
14 that uses the mux controller. Thus, a mux controller can possibly control
16 multiplexer needed by each consumer, but a single mux controller can of course
19 A mux controller provides a number of states to its consumers, and the state
[all …]
H A Dmux-consumer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common multiplexer controller consumer
10 - Peter Rosin <peda@axentia.se>
13 Mux controller consumers should specify a list of mux controllers that they
14 want to use with a property containing a 'mux-ctrl-list':
16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
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H A Dadi,adg792a.txt4 - compatible : "adi,adg792a" or "adi,adg792g"
5 - #mux-control-cells : <0> if parallel (the three muxes are bound together
6 with a single mux controller controlling all three muxes), or <1> if
7 not (one mux controller for each mux).
8 * Standard mux-controller bindings as described in mux-controller.yaml
11 - gpio-controller : if present, #gpio-cells below is required.
12 - #gpio-cells : should be <2>
13 - First cell is the GPO line number, i.e. 0 or 1
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, array of states that the mux controllers will have
[all …]
H A Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
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H A Dadi,adgs1408.txt1 Bindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux
4 - compatible : Should be one of
7 * Standard mux-controller bindings as described in mux-controller.yaml
10 - gpio-controller : if present, #gpio-cells is required.
11 - #gpio-cells : should be <2>
12 - First cell is the GPO line number, i.e. 0 to 3
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, the state that the mux controller will have
28 * One mux controller.
29 * Mux state set to idle as is (no idle-state declared)
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/openbmc/linux/include/linux/mux/
H A Ddriver.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mux/driver.h - definitions for the multiplexer driver interface
13 #include <dt-bindings/mux/mux.h>
22 * struct mux_control_ops - Mux controller operations for a mux chip.
23 * @set: Set the state of the given mux controller.
26 int (*set)(struct mux_control *mux, int state);
30 * struct mux_control - Represents a mux controller.
31 * @lock: Protects the mux controller state.
32 * @chip: The mux chip that is handling this mux controller.
33 * @cached_state: The current mux controller state, or -1 if none.
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/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-wpcm450.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
27 compatible = "arm,arm926ej-s";
33 clk24m: clock-24mhz {
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dmmp3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
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H A Dmmp2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
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/openbmc/linux/Documentation/devicetree/bindings/iio/multiplexer/
H A Dio-channel-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/multiplexer/io-channel-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
16 For each non-empty string in the channels property, an io-channel will be
17 created. The number of this io-channel is the same as the index into the list
18 of strings in the channels property, and also matches the mux controller
19 state. The mux controller state is described in
20 Documentation/devicetree/bindings/mux/mux-controller.yaml
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/openbmc/u-boot/arch/arm/dts/
H A Dmeson-axg.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
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/openbmc/linux/drivers/spi/
H A Dspi-mux.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/mux/consumer.h>
12 #define SPI_MUX_NO_CS ((unsigned int)-1)
17 * This driver supports a MUX on an SPI bus. This can be useful when you need
21 * The driver will create an additional SPI controller. Devices added under the
22 * mux will be handled as 'chip selects' on this controller.
26 * struct spi_mux_priv - the basic spi_mux structure
28 * spi controller
29 * @current_cs: The current chip select set in the mux
30 * @child_msg_complete: The mux replaces the complete callback in the child's
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmrvl,intc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP/Orion Interrupt controller
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
14 - if:
19 const: marvell,orion-intc
22 - mrvl,intc-nr-irqs
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/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-axg.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mux-gpmux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: General Purpose I2C Bus Mux
10 - Peter Rosin <peda@axentia.se>
13 This binding describes an I2C bus multiplexer that uses a mux controller
14 from the mux subsystem to route the I2C signals.
16 .-----. .-----.
18 .------------. '-----' '-----'
[all …]
H A Di2c-mux-pca954x.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-pca954x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
23 - enum:
24 - maxim,max7356
25 - maxim,max7357
26 - maxim,max7358
27 - maxim,max7367
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/openbmc/linux/drivers/mux/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
10 #define pr_fmt(fmt) "mux-core: " fmt
19 #include <linux/mux/consumer.h>
20 #include <linux/mux/driver.h>
25 * The idle-as-is "state" is not an actual state that may be selected, it
32 * struct mux_state - Represents a mux controller state specific to a given
34 * @mux: Pointer to a mux controller.
35 * @state: State of the mux to be selected.
41 struct mux_control *mux; member
46 .name = "mux",
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H A Dadg792a.c1 // SPDX-License-Identifier: GPL-2.0
3 * Multiplexer driver for Analog Devices ADG792A/G Triple 4:1 mux
13 #include <linux/mux/driver.h>
18 #define ADG792A_DISABLE(mux) (0x50 | (mux)) argument
20 #define ADG792A_MUX(mux, state) (0xc0 | (((mux) + 1) << 2) | (state)) argument
34 static int adg792a_set(struct mux_control *mux, int state) in adg792a_set() argument
36 struct i2c_client *i2c = to_i2c_client(mux->chip->dev.parent); in adg792a_set()
39 if (mux->chip->controllers == 1) { in adg792a_set()
40 /* parallel mux controller operation */ in adg792a_set()
46 unsigned int controller = mux_control_get_index(mux); in adg792a_set() local
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/openbmc/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx-iomuxc-gpr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx-iomuxc-gpr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale IOMUX Controller General Purpose Registers
10 - Peng Fan <peng.fan@nxp.com>
19 - items:
20 - const: fsl,imx8mq-iomuxc-gpr
21 - const: syscon
22 - const: simple-mfd
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmt8186-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek AFE PCM controller for mt8186
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
14 const: mediatek,mt8186-sound
25 reset-names:
30 description: The phandle of the mediatek apmixedsys controller
34 description: The phandle of the mediatek infracfg controller
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dcortina,gemini-pinctrl.txt1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
5 controller.
7 The pin controller node must be a subnode of the system controller node.
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
19 - skew-delay is supported on the Ethernet pins
20 - drive-strength with 4, 8, 12 or 16 mA as argument is supported for
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dti,j721e-system-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@ti.com>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dhdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-tx-8084
17 - qcom,hdmi-tx-8660
18 - qcom,hdmi-tx-8960
19 - qcom,hdmi-tx-8974
20 - qcom,hdmi-tx-8994
21 - qcom,hdmi-tx-8996
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dst,stm32-pinctrl.txt1 * STM32 GPIO and Pin Mux/Config controller
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
4 controller. It controls the input/output settings on the available pins and
5 also provides ability to multiplex and configure the output of various on-chip
8 Pin controller node:
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 (b) "st,stm32f746-pinctrl"
13 - #address-cells: The value of this property must be 1
14 - #size-cells : The value of this property must be 1
[all …]
/openbmc/linux/Documentation/i2c/
H A Di2c-sysfs.rst1 .. SPDX-License-Identifier: GPL-2.0
10 I2C topology can be complex because of the existence of I2C MUX
12 kernel abstracts the MUX channels into logical I2C bus numbers. However, there
13 is a gap of knowledge to map from the I2C bus physical number and MUX topology
18 useful and essential to use ``i2c-tools`` for the purpose of development and
22 ---------------
28 -------------
32 2. General knowledge of I2C, I2C MUX and I2C topology.
41 start with ``i2c-`` are I2C buses, which may be either physical or logical. The
48 0-0008 0-0061 1-0028 3-0043 4-0036 4-0041 i2c-1 i2c-3
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