| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
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| H A D | hisilicon-histb-pcie.txt | 6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
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| H A D | altera-pcie-msi.txt | 1 * Altera PCIe MSI controller
4 - compatible: should contain "altr,msi-1.0"
5 - reg: specifies the physical base address of the controller and
7 - reg-names: must include the following entries:
10 - interrupts: specifies the interrupt source of the parent interrupt
11 controller. The format of the interrupt specifier depends on the
13 - num-vectors: number of vectors, range 1 to 32.
14 - msi-controller: indicates that this is MSI controller node
18 msi0: msi@0xFF200000 {
19 compatible = "altr,msi-1.0";
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| H A D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: cdns-pcie-host.yaml#
19 - const: ti,j721e-pcie-host
20 - description: PCIe controller in AM64
22 - const: ti,am64-pcie-host
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| H A D | altera-pcie.txt | 4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 For "altr,pcie-root-port-2.0", additional HIP base address and length.
7 - reg-names: must include the following entries:
10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11 - interrupts: specifies the interrupt source of the parent interrupt
12 controller. The format of the interrupt specifier depends
14 - device_type: must be "pci"
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
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| H A D | xlnx,nwl-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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| H A D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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| H A D | mediatek-pcie.txt | 4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
13 - reg-names: Names of the above areas to use during resource lookup.
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | msi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MSI controller
10 - Marc Zyngier <maz@kernel.org>
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
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| H A D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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| /openbmc/linux/Documentation/devicetree/bindings/misc/ |
| H A D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
35 For generic MSI bindings, see
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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| /openbmc/linux/drivers/of/ |
| H A D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
31 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
50 * of_irq_find_parent - Given a device node, find its interrupt parent node
65 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
75 } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL); in of_irq_find_parent()
82 * These interrupt controllers abuse interrupt-map for unspeakable
85 * non-sensical interrupt-map that is better left ignored.
92 "CBEA,platform-spider-pic",
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| H A D | base.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1996-2005 Paul Mackerras.
66 node_name = kbasename(np->full_name); in of_node_name_eq()
67 len = strchrnul(node_name, '@') - node_name; in of_node_name_eq()
78 return strncmp(kbasename(np->full_name), prefix, strlen(prefix)) == 0; in of_node_name_prefix()
93 for (; np; np = np->parent) in of_bus_n_addr_cells()
94 if (!of_property_read_u32(np, "#address-cells", &cells)) in of_bus_n_addr_cells()
97 /* No #address-cells property for the root node */ in of_bus_n_addr_cells()
103 if (np->parent) in of_n_addr_cells()
104 np = np->parent; in of_n_addr_cells()
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| /openbmc/linux/include/linux/ |
| H A D | irqdomain.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * irq_domain - IRQ translation domains
38 #include <linux/radix-tree.h>
54 * struct irq_fwspec - generic IRQ specifier structure
56 * @fwnode: Pointer to a firmware-specific descriptor
57 * @param_count: Number of device-specific parameters
58 * @param: Device-specific parameters
61 * pass a device-specific description of an interrupt.
74 * struct irq_domain_ops - Methods for irq_domain objects
80 * @xlate: Given a device tree node and interrupt specifier, decode
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| H A D | pci.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
60 * The PCI interface treats multi-function devices as independent
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
86 return kobject_name(&slot->kobj); in pci_slot_name()
97 /* #0-5: standard PCI resources */
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
104 /* Device-specific resources */
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-ti-sci-inta.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
15 #include <linux/msi.h>
24 #include <asm-generic/msi.h>
44 * struct ti_sci_inta_event_desc - Description of an event coming to
59 * struct ti_sci_inta_vint_desc - Description of a virtual interrupt coming out
78 * struct ti_sci_inta_irq_domain - Structure representing a TISCI based
87 * @ti_sci_id: TI-SCI device identifier
89 * @unmapped_dev_ids: Pointer to an array of TI-SCI device identifiers of
95 * generating Unmapped Event, we must use the INTA's TI-SCI
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| /openbmc/linux/include/linux/gpio/ |
| H A D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/pinctrl/pinconf-generic.h>
17 #include <asm/msi.h>
46 * struct gpio_irq_chip - GPIO interrupt controller
76 * If non-NULL, will be set as the parent of this GPIO interrupt
88 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
96 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
111 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
268 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
321 * struct gpio_chip - abstract a GPIO controller
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| /openbmc/linux/drivers/pci/controller/ |
| H A D | pci-hyperv.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * This driver acts as a paravirtual front-end for PCI Express root buses.
9 * When a PCI Express function (either an entire device or an SR-IOV
13 * VM within Hyper-V, there may seem to be no PCI bus at all in the VM
18 * to the VM using this front-end will appear at "device 0", the domain will
24 * MSI or MSI-X) associated with the functions on the bus. As interrupts are
28 * vector. This driver does not support level-triggered (line-based)
32 * The rest of this driver mostly maps PCI concepts onto underlying Hyper-V
34 * by Hyper-V is mapped into a single page of memory space, and the
37 * the PCI back-end driver in Hyper-V.
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| /openbmc/linux/include/uapi/linux/ |
| H A D | pci_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
123 /* 0x35-0x3b are reserved */
129 /* Header type 1 (PCI-to-PCI bridges) */
157 /* 0x35-0x3b is reserved */
159 /* 0x3c-0x3d are same as for htype 0 */
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| /openbmc/qemu/include/standard-headers/linux/ |
| H A D | pci_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
158 /* 0x35-0x3b is reserved */
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| /openbmc/linux/tools/lib/bpf/ |
| H A D | btf_dump.c | 1 // SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause)
4 * BTF-to-C type converter.
26 static const size_t PREFIX_CNT = sizeof(PREFIXES) - 1;
30 return lvl >= PREFIX_CNT ? PREFIXES : &PREFIXES[PREFIX_CNT - lvl]; in pfx()
45 /* per-type auxiliary state */
53 /* whether unique non-duplicate name was already assigned */
88 /* per-type auxiliary state */
91 /* per-type optional cached unique name, must be freed, if present */
95 /* topo-sorted list of dependent type definitions */
133 return btf__name_by_offset(d->btf, name_off); in btf_name_of()
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| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | mpic.c | 9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
152 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
164 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_processor_id()
182 return dcr_read(rb->dhost, reg); in _mpic_read()
185 return in_be32(rb->base + (reg >> 2)); in _mpic_read()
188 return in_le32(rb->base + (reg >> 2)); in _mpic_read()
199 dcr_write(rb->dhost, reg, value); in _mpic_write()
203 out_be32(rb->base + (reg >> 2), value); in _mpic_write()
207 out_le32(rb->base + (reg >> 2), value); in _mpic_write()
214 enum mpic_reg_type type = mpic->reg_type; in _mpic_ipi_read()
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| /openbmc/linux/Documentation/sound/ |
| H A D | alsa-configuration.rst | 2 Advanced Linux Sound Architecture - Driver Configuration guide
38 ----------
47 limiting card index for auto-loading (1-8);
49 For auto-loading more than one card, specify this option
50 together with snd-card-X aliases.
63 Module snd-pcm-oss
64 ------------------
86 regarding opening the device. When this option is non-zero,
90 Module snd-rawmidi
91 ------------------
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| /openbmc/linux/Documentation/admin-guide/ |
| H A D | kernel-parameters.txt | 5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- B
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