Searched +full:mpfs +full:- +full:clkcfg (Results 1 – 10 of 10) sorted by relevance
/openbmc/linux/arch/riscv/boot/dts/microchip/ |
H A D | mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 8 #address-cells = <2>; 9 #size-cells = <2>; 11 compatible = "microchip,mpfs"; 14 #address-cells = <1>; 15 #size-cells = <0>; 20 i-cache-block-size = <64>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | microchip,mpfs-clkcfg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, 17 user nodes by the CLKCFG node phandle and the clock index in the group, from 22 const: microchip,mpfs-clkcfg 26 - description: | 31 - description: | [all …]
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/openbmc/linux/Documentation/devicetree/bindings/rtc/ |
H A D | microchip,mfps-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Microchip PolarFire Soc (MPFS) RTC 11 - $ref: rtc.yaml# 14 - Daire McNamara <daire.mcnamara@microchip.com> 15 - Lewis Hanly <lewis.hanly@microchip.com> 20 - microchip,mpfs-rtc 27 - description: | [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/can/ |
H A D | microchip,mpfs-can.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 Microchip PolarFire SoC (MPFS) can controller 11 - Conor Dooley <conor.dooley@microchip.com> 14 - $ref: can-controller.yaml# 18 const: microchip,mpfs-can 30 - compatible 31 - reg [all …]
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/openbmc/linux/Documentation/devicetree/bindings/usb/ |
H A D | microchip,mpfs-musb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip MPFS USB Controller 10 - $ref: usb-drd.yaml# 13 - Conor Dooley <conor.dooley@microchip.com> 18 - microchip,mpfs-musb 29 interrupt-names: 31 - const: dma [all …]
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/openbmc/linux/Documentation/devicetree/bindings/spi/ |
H A D | microchip,mpfs-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 - Conor Dooley <conor.dooley@microchip.com> 17 - $ref: spi-controller.yaml# 22 - items: 23 - const: microchip,mpfs-qspi 24 - const: microchip,coreqspi-rtl-v2 25 - const: microchip,coreqspi-rtl-v2 # FPGA QSPI [all …]
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/openbmc/linux/Documentation/devicetree/bindings/i2c/ |
H A D | microchip,corei2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip MPFS I2C Controller 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 - $ref: /schemas/i2c/i2c-controller.yaml# 18 - items: 19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs 20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core 21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core [all …]
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/openbmc/linux/Documentation/devicetree/bindings/gpio/ |
H A D | microchip,mpfs-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip MPFS GPIO Controller 10 - Conor Dooley <conor.dooley@microchip.com> 15 - enum: 16 - microchip,mpfs-gpio 27 interrupt-controller: true 32 "#gpio-cells": [all …]
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/openbmc/linux/drivers/clk/microchip/ |
H A D | clk-mpfs.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. 8 #include <linux/clk-provider.h> 13 #include <dt-bindings/clock/microchip,mpfs-clock.h> 14 #include <soc/microchip/mpfs.h> 67 * mpfs clk block while a software locked register is being written. 99 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate() 100 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate() 101 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; in mpfs_clk_msspll_recalc_rate() 117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_round_rate() [all …]
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/openbmc/linux/ |
H A D | opengrok1.0.log | 1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' 2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms) 3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa [all...] |