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/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Daltr,rst-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/altr,rst-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
15 - description: Cyclone5/Arria5/Arria10
16 const: altr,rst-mgr
17 - description: Stratix10 ARM64 SoC
19 - const: altr,stratix10-rst-mgr
20 - const: altr,rst-mgr
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/openbmc/linux/drivers/reset/
H A Dreset-socfpga.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copied from reset-sunxi.c
13 #include <linux/reset-controller.h>
14 #include <linux/reset/reset-simple.h>
32 return -ENOMEM; in a10_reset_init()
39 if (!request_mem_region(res.start, size, np->name)) { in a10_reset_init()
40 ret = -EBUSY; in a10_reset_init()
44 data->membase = ioremap(res.start, size); in a10_reset_init()
45 if (!data->membase) { in a10_reset_init()
46 ret = -ENOMEM; in a10_reset_init()
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/openbmc/u-boot/drivers/reset/
H A Dreset-socfpga.c1 // SPDX-License-Identifier: GPL-2.0+
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 #include <reset-uclass.h>
32 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); in socfpga_reset_assert()
33 int id = reset_ctl->id; in socfpga_reset_assert()
36 int offset = id % (reg_width * BITS_PER_BYTE); in socfpga_reset_assert() local
38 setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); in socfpga_reset_assert()
44 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); in socfpga_reset_deassert()
45 int id = reset_ctl->id; in socfpga_reset_deassert()
48 int offset = id % (reg_width * BITS_PER_BYTE); in socfpga_reset_deassert() local
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/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_swvp.dts1 // SPDX-License-Identifier: GPL-2.0
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
49 enable-method = "spin-table";
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/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53", "arm,armv8";
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H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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H A Dsocfpga_arria10.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 tick-timer = &timer2;
26 u-boot,dm-pre-reloc;
30 #address-cells = <1>;
31 #size-cells = <0>;
32 enable-method = "altr,socfpga-a10-smp";
35 compatible = "arm,cortex-a9";
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/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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