Home
last modified time | relevance | path

Searched full:mode (Results 1 – 25 of 2848) sorted by relevance

12345678910>>...114

/openbmc/qemu/tests/qemu-iotests/
H A D142.out38 Cache mode: writeback, direct
39 Cache mode: writeback, direct
40 Cache mode: writeback, direct
41 Cache mode: writeback, direct
42 Cache mode: writeback, direct
45 Cache mode: writeback
46 Cache mode: writeback
47 Cache mode: writeback, direct
48 Cache mode: writeback
49 Cache mode: writeback
[all …]
/openbmc/u-boot/board/ti/ks2_evm/
H A Dmux-k2g.h17 { 115, MODE(0) }, /* SOC_UART0_RXD */
18 { 116, MODE(0) }, /* SOC_UART0_TXD */
21 { 223, MODE(0) }, /* SOC_I2C0_SCL */
22 { 224, MODE(0) }, /* SOC_I2C0_SDA */
25 { 225, MODE(0) }, /* SOC_I2C1_SCL */
26 { 226, MODE(0) }, /* SOC_I2C1_SDA */
32 { 0, MODE(0) }, /* GPMCAD0 */
33 { 1, MODE(0) }, /* GPMCAD1 */
34 { 2, MODE(0) }, /* GPMCAD2 */
35 { 3, MODE(0) }, /* GPMCAD3 */
[all …]
/openbmc/u-boot/board/siemens/draco/
H A Dmux.c22 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
23 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
28 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
29 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
34 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
36 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
42 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
43 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
44 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
45 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
[all …]
/openbmc/u-boot/board/siemens/rut/
H A Dmux.c22 {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */
23 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
28 {OFFSET(ddr_resetn), (MODE(0))},
29 {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
30 {OFFSET(ddr_ck), (MODE(0))},
31 {OFFSET(ddr_nck), (MODE(0))},
32 {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
33 {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
34 {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
35 {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/gphoto2/libgphoto2/
H A D40-libgphoto2.rules10 ATTRS{idVendor}=="0979", ATTRS{idProduct}=="0227", MODE="l36"
11 ATTRS{idVendor}=="0502", ATTRS{idProduct}=="33c3", ENV{ID_MEDIA_PLAYER}="1", MODE="l36"
12 ATTRS{idVendor}=="0502", ATTRS{idProduct}=="33c4", ENV{ID_MEDIA_PLAYER}="1", MODE="l36"
13 ATTRS{idVendor}=="0502", ATTRS{idProduct}=="3643", ENV{ID_MEDIA_PLAYER}="1", MODE="l36"
14 ATTRS{idVendor}=="0502", ATTRS{idProduct}=="353c", ENV{ID_MEDIA_PLAYER}="1", MODE="l36"
15 ATTRS{idVendor}=="0502", ATTRS{idProduct}=="362d", ENV{ID_MEDIA_PLAYER}="1", MODE="l36"
16 ATTRS{idVendor}=="0502", ATTRS{idProduct}=="3586", ENV{ID_MEDIA_PLAYER}="1", MODE="l36"
17 ATTRS{idVendor}=="0502", ATTRS{idProduct}=="3348", ENV{ID_MEDIA_PLAYER}="1", MODE="l36"
18 ATTRS{idVendor}=="0502", ATTRS{idProduct}=="3349", ENV{ID_MEDIA_PLAYER}="1", MODE="l36"
19 ATTRS{idVendor}=="0502", ATTRS{idProduct}=="334a", ENV{ID_MEDIA_PLAYER}="1", MODE="l36"
[all …]
/openbmc/u-boot/board/siemens/pxm2/
H A Dmux.c23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
25 {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
31 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
32 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
33 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
34 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
35 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
36 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
37 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
[all …]
/openbmc/u-boot/board/bosch/shc/
H A Dmux.c21 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */
22 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
23 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */
24 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */
29 {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */
30 {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */
31 {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */
32 {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */
37 {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */
38 {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */
[all …]
/openbmc/u-boot/board/compulab/cm_t43/
H A Dmux.c12 {OFFSET(mii1_txen), MODE(2)},
13 {OFFSET(mii1_txd3), MODE(2)},
14 {OFFSET(mii1_txd2), MODE(2)},
15 {OFFSET(mii1_txd1), MODE(2)},
16 {OFFSET(mii1_txd0), MODE(2)},
17 {OFFSET(mii1_txclk), MODE(2)},
18 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN},
19 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN},
20 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN},
21 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN},
[all …]
/openbmc/u-boot/board/BuR/brppt1/
H A Dmux.c20 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
22 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
24 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
31 {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
33 {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
35 {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
37 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
42 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
43 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
[all …]
/openbmc/u-boot/board/ti/am335x/
H A Dmux.c26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
[all …]
/openbmc/u-boot/board/BuR/brxre1/
H A Dmux.c20 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
22 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
24 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
26 {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
28 {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
34 {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
36 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
42 {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
44 {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
50 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
[all …]
/openbmc/u-boot/board/ti/am43xx/
H A Dmux.c15 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
16 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
17 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
18 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
19 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
20 {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
21 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
22 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
23 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
28 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
[all …]
/openbmc/u-boot/board/birdland/bav335x/
H A Dmux.c26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
[all …]
/openbmc/u-boot/board/compulab/cm_t335/
H A Dmux.c17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
23 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
24 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
25 {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
26 {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
31 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
32 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
33 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
34 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
[all …]
/openbmc/u-boot/board/vscom/baltos/
H A Dmux.c25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
31 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
32 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
33 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
34 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
35 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
36 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
41 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
43 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
[all …]
/openbmc/u-boot/board/silica/pengwyn/
H A Dmux.c17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
26 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
28 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
35 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
36 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
37 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
38 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
39 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
40 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
[all …]
/openbmc/u-boot/board/tcl/sl50/
H A Dmux.c17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
23 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
24 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
29 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
30 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
35 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
36 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
41 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
42 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
[all …]
/openbmc/u-boot/board/phytec/pcm051/
H A Dmux.c25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
32 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
33 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
34 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
35 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
36 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
37 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
38 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
45 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
[all …]
/openbmc/u-boot/board/ti/ti814x/
H A Dmux.c25 {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */
26 {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */
31 {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
32 {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
33 {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */
34 {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */
35 {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */
36 {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */
37 {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */
38 {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
[all …]
/openbmc/openbmc/poky/bitbake/lib/bb/compress/
H A D_pipecompress.py19 cls, filename, mode="rb", *, encoding=None, errors=None, newline=None, **kwargs argument
22 Open a compressed file in binary or text mode.
30 The mode argument can be "r", "rb", "w", "wb", "x", "xb", "a" or "ab" for
31 binary mode, or "rt", "wt", "xt" or "at" for text mode. The default mode is
34 For binary mode, this function is equivalent to the cls constructor:
35 cls(filename, mode). In this case, the encoding, errors and newline
38 For text mode, a cls object is created, and wrapped in an
42 if "t" in mode:
43 if "b" in mode:
44 raise ValueError("Invalid mode: %r" % (mode,))
[all …]
/openbmc/u-boot/drivers/video/
H A Dati_radeon_fb.c198 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) in radeon_write_pll_regs() argument
214 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
215 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
221 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
241 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
249 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { in radeon_write_pll_regs()
250 /* When restoring console mode, use saved PPLL_REF_DIV in radeon_write_pll_regs()
253 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
257 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), in radeon_write_pll_regs()
261 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
[all …]
H A Dmxsfb.c30 * needed when driving the controller in System-Mode to operate an 8080 or
40 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
45 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
50 struct ctfb_res_modes *mode, int bpp) in mxs_lcd_init() argument
57 mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock)); in mxs_lcd_init()
94 writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres, in mxs_lcd_init()
100 mode->vsync_len, &regs->hw_lcdif_vdctrl0); in mxs_lcd_init()
101 writel(mode->upper_margin + mode->lower_margin + in mxs_lcd_init()
102 mode->vsync_len + mode->yres, in mxs_lcd_init()
104 writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) | in mxs_lcd_init()
[all …]
/openbmc/u-boot/board/isee/igep003x/
H A Dmux.c23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
29 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
30 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
31 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
32 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
33 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
34 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
35 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
40 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
[all …]
/openbmc/u-boot/board/gumstix/pepper/
H A Dmux.c16 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
17 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
22 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
23 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
24 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
25 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
26 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
27 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
28 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
34 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
[all …]
/openbmc/qemu/hw/display/
H A Dbochs-display.c56 BochsDisplayMode mode; member
155 BochsDisplayMode *mode) in bochs_display_get_mode() argument
164 memset(mode, 0, sizeof(*mode)); in bochs_display_get_mode()
168 mode->format = PIXMAN_r5g6b5; in bochs_display_get_mode()
169 mode->bytepp = 2; in bochs_display_get_mode()
172 mode->format = s->big_endian_fb in bochs_display_get_mode()
175 mode->bytepp = 4; in bochs_display_get_mode()
181 mode->width = vbe[VBE_DISPI_INDEX_XRES]; in bochs_display_get_mode()
182 mode->height = vbe[VBE_DISPI_INDEX_YRES]; in bochs_display_get_mode()
184 if (virt_width < mode->width) { in bochs_display_get_mode()
[all …]

12345678910>>...114