| /openbmc/linux/drivers/staging/media/ipu3/ |
| H A D | ipu3-mmu.c | 21 #include "ipu3-mmu.h"
73 * @mmu: MMU to perform the invalidate operation on
78 static void imgu_mmu_tlb_invalidate(struct imgu_mmu *mmu) in imgu_mmu_tlb_invalidate() argument
80 writel(TLB_INVALIDATE, mmu->base + REG_TLB_INVALIDATE); in imgu_mmu_tlb_invalidate()
83 static void call_if_imgu_is_powered(struct imgu_mmu *mmu, in call_if_imgu_is_powered() argument
84 void (*func)(struct imgu_mmu *mmu)) in call_if_imgu_is_powered() argument
86 if (!pm_runtime_get_if_in_use(mmu->dev)) in call_if_imgu_is_powered()
89 func(mmu); in call_if_imgu_is_powered()
90 pm_runtime_put(mmu->dev); in call_if_imgu_is_powered()
95 * @mmu: MMU to set the CIO gate bit in.
[all …]
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvif/ |
| H A D | mmu.c | 22 #include <nvif/mmu.h>
28 nvif_mmu_dtor(struct nvif_mmu *mmu) in nvif_mmu_dtor() argument
30 if (!nvif_object_constructed(&mmu->object)) in nvif_mmu_dtor()
33 kfree(mmu->kind); in nvif_mmu_dtor()
34 kfree(mmu->type); in nvif_mmu_dtor()
35 kfree(mmu->heap); in nvif_mmu_dtor()
36 nvif_object_dtor(&mmu->object); in nvif_mmu_dtor()
41 struct nvif_mmu *mmu) in nvif_mmu_ctor() argument
53 mmu->heap = NULL; in nvif_mmu_ctor()
54 mmu->type = NULL; in nvif_mmu_ctor()
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ |
| H A D | Kbuild | 2 nvkm-y += nvkm/subdev/mmu/base.o
3 nvkm-y += nvkm/subdev/mmu/nv04.o
4 nvkm-y += nvkm/subdev/mmu/nv41.o
5 nvkm-y += nvkm/subdev/mmu/nv44.o
6 nvkm-y += nvkm/subdev/mmu/nv50.o
7 nvkm-y += nvkm/subdev/mmu/g84.o
8 nvkm-y += nvkm/subdev/mmu/mcp77.o
9 nvkm-y += nvkm/subdev/mmu/gf100.o
10 nvkm-y += nvkm/subdev/mmu/gk104.o
11 nvkm-y += nvkm/subdev/mmu/gk20a.o
[all …]
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| H A D | base.c | 42 nvkm_mmu_ptp_put(struct nvkm_mmu *mmu, bool force, struct nvkm_mmu_pt *pt) in nvkm_mmu_ptp_put() argument
51 list_add(&ptp->head, &mmu->ptp.list); in nvkm_mmu_ptp_put()
56 nvkm_mmu_ptc_put(mmu, force, &ptp->pt); in nvkm_mmu_ptp_put()
65 nvkm_mmu_ptp_get(struct nvkm_mmu *mmu, u32 size, bool zero) in nvkm_mmu_ptp_get() argument
74 ptp = list_first_entry_or_null(&mmu->ptp.list, typeof(*ptp), head); in nvkm_mmu_ptp_get()
82 ptp->pt = nvkm_mmu_ptc_get(mmu, 0x1000, 0x1000, false); in nvkm_mmu_ptp_get()
93 list_add(&ptp->head, &mmu->ptp.list); in nvkm_mmu_ptp_get()
120 nvkm_mmu_ptc_find(struct nvkm_mmu *mmu, u32 size) in nvkm_mmu_ptc_find() argument
124 list_for_each_entry(ptc, &mmu->ptc.list, head) { in nvkm_mmu_ptc_find()
134 list_add(&ptc->head, &mmu->ptc.list); in nvkm_mmu_ptc_find()
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| H A D | ummu.c | 35 struct nvkm_mmu *mmu = nvkm_ummu(object)->mmu; in nvkm_ummu_sclass() local
37 if (mmu->func->mem.user.oclass) { in nvkm_ummu_sclass()
39 oclass->base = mmu->func->mem.user; in nvkm_ummu_sclass()
45 if (mmu->func->vmm.user.oclass) { in nvkm_ummu_sclass()
47 oclass->base = mmu->func->vmm.user; in nvkm_ummu_sclass()
59 struct nvkm_mmu *mmu = ummu->mmu; in nvkm_ummu_heap() local
67 if ((index = args->v0.index) >= mmu->heap_nr) in nvkm_ummu_heap()
69 args->v0.size = mmu->heap[index].size; in nvkm_ummu_heap()
79 struct nvkm_mmu *mmu = ummu->mmu; in nvkm_ummu_type() local
87 if ((index = args->v0.index) >= mmu->type_nr) in nvkm_ummu_type()
[all …]
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| /openbmc/linux/drivers/staging/media/atomisp/pci/mmu/ |
| H A D | isp_mmu.c | 21 * ISP MMU management wrap code
41 #include "mmu/isp_mmu.h"
51 * that are only 32-bit capable(e.g. the ISP MMU).
57 static void free_mmu_map(struct isp_mmu *mmu, unsigned int start_isp_virt,
79 static phys_addr_t isp_pte_to_pgaddr(struct isp_mmu *mmu, in isp_pte_to_pgaddr() argument
82 return mmu->driver->pte_to_phys(mmu, pte); in isp_pte_to_pgaddr()
85 static unsigned int isp_pgaddr_to_pte_valid(struct isp_mmu *mmu, in isp_pgaddr_to_pte_valid() argument
88 unsigned int pte = mmu->driver->phys_to_pte(mmu, phys); in isp_pgaddr_to_pte_valid()
90 return (unsigned int)(pte | ISP_PTE_VALID_MASK(mmu)); in isp_pgaddr_to_pte_valid()
97 static phys_addr_t alloc_page_table(struct isp_mmu *mmu) in alloc_page_table() argument
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| /openbmc/qemu/target/microblaze/ |
| H A D | mmu.c | 2 * Microblaze MMU emulation for qemu.
40 MicroBlazeMMU *mmu = &env->mmu; in mmu_flush_idx() local
44 t = mmu->rams[RAM_TAG][idx]; in mmu_flush_idx()
60 MicroBlazeMMU *mmu = &env->mmu; in mmu_change_pid() local
67 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { in mmu_change_pid()
69 t = mmu->rams[RAM_TAG][i]; in mmu_change_pid()
71 if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i])) in mmu_change_pid()
81 MicroBlazeMMU *mmu = &cpu->env.mmu; in mmu_translate() local
88 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { in mmu_translate()
92 t = mmu->rams[RAM_TAG][i]; in mmu_translate()
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| /openbmc/linux/drivers/iommu/ |
| H A D | ipmmu-vmsa.c | 72 struct ipmmu_vmsa_device *mmu; member
100 /* MMU "context" registers */
150 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu) in ipmmu_is_root() argument
152 return mmu->root == mmu; in ipmmu_is_root()
157 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); in __ipmmu_check_device() local
160 if (ipmmu_is_root(mmu)) in __ipmmu_check_device()
161 *rootp = mmu; in __ipmmu_check_device()
178 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset) in ipmmu_read() argument
180 return ioread32(mmu->base + offset); in ipmmu_read()
183 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset, in ipmmu_write() argument
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| /openbmc/linux/arch/x86/kernel/ |
| H A D | paravirt.c | 231 /* Mmu ops. */
232 .mmu.flush_tlb_user = native_flush_tlb_local,
233 .mmu.flush_tlb_kernel = native_flush_tlb_global,
234 .mmu.flush_tlb_one_user = native_flush_tlb_one_user,
235 .mmu.flush_tlb_multi = native_flush_tlb_multi,
236 .mmu.tlb_remove_table = native_tlb_remove_table,
238 .mmu.exit_mmap = paravirt_nop,
239 .mmu.notify_page_enc_status_changed = paravirt_nop,
242 .mmu.read_cr2 = __PV_IS_CALLEE_SAVE(pv_native_read_cr2),
243 .mmu.write_cr2 = pv_native_write_cr2,
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| /openbmc/linux/drivers/gpu/drm/panfrost/ |
| H A D | panfrost_mmu.c | 34 /* Wait for the MMU status to indicate there is no active command, in in wait_ready()
52 /* write AS_COMMAND when MMU is ready to accept another command */ in write_cmd()
105 /* Run the MMU operation */ in mmu_hw_do_operation_locked()
113 struct panfrost_mmu *mmu, in mmu_hw_do_operation() argument
119 ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op); in mmu_hw_do_operation()
124 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) in panfrost_mmu_enable() argument
126 int as_nr = mmu->as; in panfrost_mmu_enable()
127 struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg; in panfrost_mmu_enable()
158 u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) in panfrost_mmu_as_get() argument
164 as = mmu->as; in panfrost_mmu_as_get()
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| /openbmc/linux/drivers/staging/media/atomisp/include/mmu/ |
| H A D | isp_mmu.h | 21 * ISP MMU driver for classic two-level page tables
88 unsigned int (*get_pd_base)(struct isp_mmu *mmu, phys_addr_t pd_base);
100 void (*tlb_flush_range)(struct isp_mmu *mmu,
102 void (*tlb_flush_all)(struct isp_mmu *mmu);
103 unsigned int (*phys_to_pte)(struct isp_mmu *mmu,
105 phys_addr_t (*pte_to_phys)(struct isp_mmu *mmu,
120 #define ISP_PTE_VALID_MASK(mmu) \ argument
121 ((mmu)->driver->pte_valid_mask)
123 #define ISP_PTE_VALID(mmu, pte) \ argument
124 ((pte) & ISP_PTE_VALID_MASK(mmu))
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| /openbmc/linux/drivers/accel/ivpu/ |
| H A D | ivpu_mmu.c | 213 return "MMU bypass is disallowed for this StreamID"; in ivpu_mmu_event_to_str()
255 ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
259 ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF); in ivpu_mmu_config_check()
263 ivpu_dbg(vdev, MMU, "IDR3 0x%x != IDR3_REF 0x%x\n", val, IVPU_MMU_IDR3_REF); in ivpu_mmu_config_check()
274 ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
279 struct ivpu_mmu_info *mmu = vdev->mmu; in ivpu_mmu_cdtab_alloc() local
280 struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab; in ivpu_mmu_cdtab_alloc()
287 ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size); in ivpu_mmu_cdtab_alloc()
294 struct ivpu_mmu_info *mmu = vdev->mmu; in ivpu_mmu_strtab_alloc() local
295 struct ivpu_mmu_strtab *strtab = &mmu->strtab; in ivpu_mmu_strtab_alloc()
[all …]
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| /openbmc/linux/arch/m68k/ |
| H A D | Kconfig.cpu | 6 default M68KCLASSIC if MMU
7 default COLDFIRE if !MMU
40 depends on !MMU
54 a paging MMU.
58 depends on MMU
64 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
69 depends on MMU && !MMU_SUN3
75 work, as it does not include an MMU (Memory Management Unit).
79 depends on MMU && !MMU_SUN3
85 MC68EC040 will not work, as it does not include an MMU (Memory
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| H A D | Kconfig | 7 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
9 select ARCH_HAS_DMA_PREP_COHERENT if HAS_DMA && MMU && !COLDFIRE
17 select DMA_DIRECT_REMAP if HAS_DMA && MMU && !COLDFIRE
30 select MMU_GATHER_NO_RANGE if MMU
33 select NO_DMA if !MMU && !COLDFIRE
36 select UACCESS_MEMCPY if !MMU
75 config MMU config
76 bool "MMU-based Paged Memory Management Support"
79 Select if you want MMU-based virtualised addressing space
90 depends on MMU && !MMU_MOTOROLA && !MMU_COLDFIRE
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| H A D | Kconfig.machine | 8 depends on MMU
9 select MMU_MOTOROLA if MMU
18 depends on MMU
19 select MMU_MOTOROLA if MMU
33 depends on MMU
34 select MMU_MOTOROLA if MMU
46 depends on MMU
47 select MMU_MOTOROLA if MMU
55 depends on MMU
56 select MMU_MOTOROLA if MMU
[all …]
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| /openbmc/linux/drivers/gpu/drm/msm/ |
| H A D | msm_mmu.h | 13 void (*detach)(struct msm_mmu *mmu);
14 int (*map)(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt,
16 int (*unmap)(struct msm_mmu *mmu, uint64_t iova, size_t len);
17 void (*destroy)(struct msm_mmu *mmu);
18 void (*resume_translation)(struct msm_mmu *mmu);
35 static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev, in msm_mmu_init() argument
38 mmu->dev = dev; in msm_mmu_init()
39 mmu->funcs = funcs; in msm_mmu_init()
40 mmu->type = type; in msm_mmu_init()
47 static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, in msm_mmu_set_fault_handler() argument
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| H A D | msm_iommu.c | 30 static struct msm_iommu_pagetable *to_pagetable(struct msm_mmu *mmu) in to_pagetable() argument
32 return container_of(mmu, struct msm_iommu_pagetable, base); in to_pagetable()
91 static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, in msm_iommu_pagetable_unmap() argument
94 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); in msm_iommu_pagetable_unmap()
115 static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova, in msm_iommu_pagetable_map() argument
118 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); in msm_iommu_pagetable_map()
145 msm_iommu_pagetable_unmap(mmu, iova, addr - iova); in msm_iommu_pagetable_map()
154 static void msm_iommu_pagetable_destroy(struct msm_mmu *mmu) in msm_iommu_pagetable_destroy() argument
156 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); in msm_iommu_pagetable_destroy()
172 int msm_iommu_pagetable_params(struct msm_mmu *mmu, in msm_iommu_pagetable_params() argument
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| /openbmc/linux/arch/arm/mm/ |
| H A D | Kconfig | 11 depends on !MMU
30 select CPU_COPY_V4WT if MMU
34 select CPU_TLB_V4WT if MMU
37 MMU built around an ARM7TDMI core.
45 depends on !MMU
63 depends on !MMU
82 select CPU_COPY_V4WB if MMU
86 select CPU_TLB_V4WBI if MMU
101 select CPU_COPY_V4WB if MMU
105 select CPU_TLB_V4WBI if MMU
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| /openbmc/linux/arch/arc/mm/ |
| H A D | tlb.c | 16 #include <asm/mmu.h>
87 * If Not already present get a free slot from MMU. in tlb_entry_insert()
99 * Commit the Entry to MMU in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
136 struct cpuinfo_arc_mmu *mmu = &mmuinfo; in local_flush_tlb_all() local
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
182 * Only for fork( ) do we need to move parent to a new MMU ctxt, in local_flush_tlb_mm()
245 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
274 * Delete TLB entry in MMU for a given page (??? address)
403 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr) in create_tlb()
[all …]
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| /openbmc/linux/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/ |
| H A D | mmu_public.h | 23 /*! Set the page table base index of MMU[ID]
25 \param ID[in] MMU identifier
28 \return none, MMU[ID].page_table_base_index = base_index
34 /*! Get the page table base index of MMU[ID]
36 \param ID[in] MMU identifier
39 \return MMU[ID].page_table_base_index
44 /*! Invalidate the page table cache of MMU[ID]
46 \param ID[in] MMU identifier
59 /*! Write to a control register of MMU[ID]
61 \param ID[in] MMU identifier
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| /openbmc/linux/arch/x86/include/asm/ |
| H A D | paravirt.h | 71 PVOP_VCALL0(mmu.flush_tlb_user); in __flush_tlb_local()
76 PVOP_VCALL0(mmu.flush_tlb_kernel); in __flush_tlb_global()
81 PVOP_VCALL1(mmu.flush_tlb_one_user, addr); in __flush_tlb_one_user()
87 PVOP_VCALL2(mmu.flush_tlb_multi, cpumask, info); in __flush_tlb_multi()
92 PVOP_VCALL2(mmu.tlb_remove_table, tlb, table); in paravirt_tlb_remove_table()
97 PVOP_VCALL1(mmu.exit_mmap, mm); in paravirt_arch_exit_mmap()
103 PVOP_VCALL3(mmu.notify_page_enc_status_changed, pfn, npages, enc); in notify_page_enc_status_changed()
144 return PVOP_ALT_CALLEE0(unsigned long, mmu.read_cr2, in read_cr2()
151 PVOP_VCALL1(mmu.write_cr2, x); in write_cr2()
156 return PVOP_ALT_CALL0(unsigned long, mmu.read_cr3, in __read_cr3()
[all …]
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| /openbmc/linux/arch/riscv/ |
| H A D | Kconfig | 23 select ARCH_HAS_DEBUG_VIRTUAL if MMU
35 select ARCH_HAS_SET_DIRECT_MAP if MMU
36 select ARCH_HAS_SET_MEMORY if MMU
37 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
38 select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL
48 select ARCH_SUPPORTS_DEBUG_PAGEALLOC if MMU
49 select ARCH_SUPPORTS_HUGETLBFS if MMU
50 select ARCH_SUPPORTS_PAGE_TABLE_CHECK if MMU
51 select ARCH_SUPPORTS_PER_VMA_LOCK if MMU
55 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
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| /openbmc/linux/arch/sh/mm/ |
| H A D | Kconfig | 4 config MMU config
9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 On other systems (such as the SH-3 and 4) where an MMU exists,
14 MMU implicitly switched off.
18 default "0x80000000" if MMU
25 default "13" if !MMU
74 default !MMU
78 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
88 depends on (CPU_SHX2 || CPU_SHX3) && MMU
92 depends on MMU && (CPU_SH3 || CPU_SH4)
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| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | samsung,sysmmu.yaml | 7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
17 System MMU is an IOMMU and supports identical translation table format to
19 permissions, shareability and security protection. In addition, System MMU has
25 master), but one System MMU can handle transactions from only one peripheral
26 device. The relation between a System MMU and the peripheral device needs to be
31 * MFC has one System MMU on its left and right bus.
32 * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
34 * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
35 the other System MMU on the write channel.
37 For information on assigning System MMU controller to its peripheral devices,
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | branch.json | 18 …still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off",
21 … still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off"
24 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
27 …r the address. This event still counts when branch prediction is disabled due to the MMU being off"
30 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
33 …d the address. This event still counts when branch prediction is disabled due to the MMU being off"
36 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
39 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
42 …he condition. This event still counts when branch prediction is disabled due to the MMU being off",
45 …the condition. This event still counts when branch prediction is disabled due to the MMU being off"
[all …]
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