2  *  Microblaze MMU emulation for qemu.
40     MicroBlazeMMU *mmu = &env->mmu;  in mmu_flush_idx()  local
44     t = mmu->rams[RAM_TAG][idx];  in mmu_flush_idx()
60     MicroBlazeMMU *mmu = &env->mmu;  in mmu_change_pid()  local
67     for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {  in mmu_change_pid()
69         t = mmu->rams[RAM_TAG][i];  in mmu_change_pid()
71             if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))  in mmu_change_pid()
81     MicroBlazeMMU *mmu = &cpu->env.mmu;  in mmu_translate()  local
88     for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {  in mmu_translate()
92         t = mmu->rams[RAM_TAG][i];  in mmu_translate()
105             if (mmu->tids[i]  in mmu_translate()
106                 && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {  in mmu_translate()
111             d = mmu->rams[RAM_DATA][i];  in mmu_translate()
117             t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));  in mmu_translate()
126             if (cpu->cfg.mmu == 1) {  in mmu_translate()
173                   "MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",  in mmu_translate()
178 /* Writes/reads to the MMU's special regs end up here.  */
185     if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) {  in mmu_read()
186         qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");  in mmu_read()
195         /* Reads to HI/LO trig reads from the mmu rams.  */  in mmu_read()
200                               "Invalid access to MMU reg %d\n", rn);  in mmu_read()
204             i = env->mmu.regs[MMU_R_TLBX] & 0xff;  in mmu_read()
205             r = extract64(env->mmu.rams[rn & 1][i], ext * 32, 32);  in mmu_read()
207                 env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];  in mmu_read()
213                               "Invalid access to MMU reg %d\n", rn);  in mmu_read()
216             r = env->mmu.regs[rn];  in mmu_read()
219             r = env->mmu.regs[rn];  in mmu_read()
225             qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);  in mmu_read()
240                   rn < 3 ? env->mmu.regs[rn] : env->mmu.regs[MMU_R_TLBX]);  in mmu_write()
242     if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) {  in mmu_write()
243         qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");  in mmu_write()
252         /* Writes to HI/LO trig writes to the mmu rams.  */  in mmu_write()
255             i = env->mmu.regs[MMU_R_TLBX] & 0xff;  in mmu_write()
261                 env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;  in mmu_write()
264             tmp64 = env->mmu.rams[rn & 1][i];  in mmu_write()
265             env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v);  in mmu_write()
270                               "Invalid access to MMU reg %d\n", rn);  in mmu_write()
276             if (v != env->mmu.regs[rn]) {  in mmu_write()
279             env->mmu.regs[rn] = v;  in mmu_write()
284                               "Invalid access to MMU reg %d\n", rn);  in mmu_write()
288             if (v != env->mmu.regs[rn]) {  in mmu_write()
290                 env->mmu.regs[rn] = v;  in mmu_write()
295             env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);  in mmu_write()
304                               "Invalid access to MMU reg %d\n", rn);  in mmu_write()
311                 env->mmu.regs[MMU_R_TLBX] = lu.idx;  in mmu_write()
313                 env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK;  in mmu_write()
318             qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);  in mmu_write()
323 void mmu_init(MicroBlazeMMU *mmu)  in mmu_init()  argument
326     for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {  in mmu_init()
327         mmu->regs[i] = 0;  in mmu_init()