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/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun6i-a31-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - enum:
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
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H A Dmipi-dsi-bus.txt1 MIPI DSI (Display Serial Interface) busses
4 The MIPI Display Serial Interface specifies a serial bus and a protocol for
6 define the syntax used to represent a DSI bus in a device tree.
8 This document describes DSI bus-specific properties only or defines existing
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
12 set of properties that characterize the bus. Child nodes describe individual
13 peripherals on that bus.
15 The following assumes that only a single peripheral is connected to a DSI
18 DSI host
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H A Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 encoder clock source and contains additional TV TCON and DSI gates.
22 / [0] TCON-LCD0
23 | \ MIPI DSI
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
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H A Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DSI host controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
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/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dmipi_dsim.h1 /* SPDX-License-Identifier: GPL-2.0+ */
62 /* MIPI DSI Processor-to-Peripheral transaction types */
111 * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
121 * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
122 * start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
126 * if this variable is set, DSI master ignores HFP area in VIDEO mode.
129 * if this variable is set, DSI master ignores HBP area in VIDEO mode.
132 * if this variable is set, DSI master ignores HSA area in VIDEO mode.
139 * in Non-burst mode, RGB data area is filled with RGB data and NULL
154 * BTA requests to D-PHY automatically. this counter value specifies
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/openbmc/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
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H A Dfsl,imx8mn-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MN DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mn-disp-blk-ctrl
21 - const: syscon
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H A Dfsl,imx8mp-media-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
26 '#address-cells':
29 '#size-cells':
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
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H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DSI to eDP Video Format Converter
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
28 powerdown-gpios:
32 reset-gpios:
36 vdd12-supply:
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/openbmc/linux/drivers/gpu/drm/
H A Ddrm_mipi_dsi.c2 * MIPI DSI Bus
4 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
21 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
42 * DOC: dsi helpers
44 * These functions contain some common logic and helpers to deal with MIPI DSI
47 * Helpers are provided for a number of standard MIPI DSI command as well as a
48 * subset of the MIPI DCS command set.
53 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in mipi_dsi_device_match() local
59 /* compare DSI device and driver names */ in mipi_dsi_device_match()
60 if (!strcmp(dsi->name, drv->name)) in mipi_dsi_device_match()
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H A Ddrm_bridge.c17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 #include <linux/media-bus-format.h>
50 * [ CRTC ---> ] Encoder ---> Bridge A ---> Bridge B
88 * drm_atomic_helper_commit_modeset_disables() (either directly in hand-rolled
89 * commit check and commit tail handlers, or through the higher-level
98 * connector-related operations exposed by the bridge (see the overview
103 * DOC: special care dsi
110 * - The upstream driver doesn't use the component framework and isn't a
111 * MIPI-DSI host. In this case, the bridge driver will probe at some
115 * - The upstream driver doesn't use the component framework, but is a
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/openbmc/linux/include/drm/
H A Ddrm_mipi_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * MIPI DSI Bus
5 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
24 * struct mipi_dsi_msg - read/write DSI buffer
49 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
67 * struct mipi_dsi_host_ops - DSI bus operations
68 * @attach: attach DSI device to DSI host
69 * @detach: detach DSI device from DSI host
70 * @transfer: transmit a DSI packet
72 * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos_mipi_dsi.txt1 Exynos MIPI-DSIM Controller
6 compatible: should be "samsung,exynos-mipi-dsi"
7 reg: Base address of MIPI-DSIM IP.
10 samsung,dsim-config-e-interface: interface to be used (RGB interface
12 samsung,dsim-config-e-virtual-ch: virtual channel number that main
14 samsung,dsim-config-e-pixel-format: pixel stream format for main
16 samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode.
17 in Non-burst mode, RGB data area is filled with RGB data and
19 samsung,dsim-config-e-no-data-lane: data lane count used by Master.
20 samsung,dsim-config-e-byte-clk: select byte clock source.
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/openbmc/linux/drivers/pmdomain/imx/
H A Dimx8m-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/power/imx8mm-power.h>
20 #include <dt-bindings/power/imx8mn-power.h>
21 #include <dt-bindings/power/imx8mp-power.h>
22 #include <dt-bindings/power/imx8mq-power.h>
51 * which is used to control the reset for the MIPI Phy.
53 * an if-statement should be used before setting and clearing this
88 const struct imx8m_blk_ctrl_domain_data *data = domain->data; in imx8m_blk_ctrl_power_on()
89 struct imx8m_blk_ctrl *bc = domain->bc; in imx8m_blk_ctrl_power_on()
92 /* make sure bus domain is awake */ in imx8m_blk_ctrl_power_on()
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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dallwinner,sun6i-a31-mipi-dphy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
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/openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
24 dispc, dsi, hdmi and rfbi.
34 <debugfs>/omapdss/dsi_irq for DSI interrupts.
46 OMAP Video Encoder support for S-Video and composite TV-out.
71 SDI is a high speed one-way display serial bus between the host
75 bool "DSI support"
77 MIPI DSI (Display Serial Interface) support.
79 DSI is a high speed half-duplex serial interface between the host
82 See https://www.mipi.org/ for DSI specifications.
/openbmc/linux/drivers/gpu/drm/omapdrm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 dispc, dsi, hdmi and rfbi.
42 <debugfs>/omapdss/dsi_irq for DSI interrupts.
54 OMAP Video Encoder support for S-Video and composite TV-out.
89 SDI is a high speed one-way display serial bus between the host
93 bool "DSI support"
97 MIPI DSI (Display Serial Interface) support.
99 DSI is a high speed half-duplex serial interface between the host
102 See http://www.mipi.org/ for DSI specifications.
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
24 #define master_to_driver(a) (a->dsim_lcd_drv)
25 #define master_to_device(a) (a->dsim_lcd_dev)
45 return -EFAULT; in exynos_mipi_dsi_register_lcd_device()
48 if (!lcd_dev->name) { in exynos_mipi_dsi_register_lcd_device()
50 return -EFAULT; in exynos_mipi_dsi_register_lcd_device()
56 return -EFAULT; in exynos_mipi_dsi_register_lcd_device()
59 dsim_ddi->dsim_lcd_dev = lcd_dev; in exynos_mipi_dsi_register_lcd_device()
61 list_add_tail(&dsim_ddi->list, &dsim_ddi_list); in exynos_mipi_dsi_register_lcd_device()
73 lcd_dev = dsim_ddi->dsim_lcd_dev; in exynos_mipi_dsi_find_lcd_device()
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/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
10 - Liu Ying <victor.liu@nxp.com>
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
14 sitting together with the PHYs. It is not the same as the MSI bus coming
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
20 connected to the bus can be accessed. Also, the bus is part of a power
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/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
9 - #size-cells: The number of cells used to represent the size of an address
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
16 - reset-names: Must include the following entries:
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/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-elida-kd35t133.c1 // SPDX-License-Identifier: GPL-2.0
3 * Elida kd35t133 5.5" MIPI-DSI panel driver
8 * Rockteck jh057n00900 5.5" MIPI-DSI panel driver
14 #include <linux/media-bus-format.h>
26 /* Manufacturer specific Commands send via DSI */
56 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in kd35t133_init_sequence() local
57 struct device *dev = ctx->dev; in kd35t133_init_sequence()
63 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_POSITIVEGAMMA, in kd35t133_init_sequence()
66 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_NEGATIVEGAMMA, in kd35t133_init_sequence()
69 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_POWERCONTROL1, 0x18, 0x17); in kd35t133_init_sequence()
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H A Dpanel-xinpeng-xpp055c272.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xinpeng xpp055c272 5.5" MIPI-DSI panel driver
8 * Rockteck jh057n00900 5.5" MIPI-DSI panel driver
21 #include <linux/media-bus-format.h>
26 /* Manufacturer specific Commands send via DSI */
65 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in xpp055c272_init_sequence() local
66 struct device *dev = ctx->dev; in xpp055c272_init_sequence()
72 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83); in xpp055c272_init_sequence()
73 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETMIPI, in xpp055c272_init_sequence()
78 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25); in xpp055c272_init_sequence()
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/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
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