| /openbmc/linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-385-clearfog-gtr.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
[all …]
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| H A D | armada-xp-axpwifiap.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Marvell RD-AXPWiFiAP.
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include "armada-xp-mv78230.dtsi"
21 model = "Marvell RD-AXPWiFiAP";
22 …compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,arma…
25 stdout-path = "serial0:115200n8";
[all …]
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| H A D | dove-sbc-a510.dts | 2 * Device Tree file for Compulab SBC-A510 Single Board Computer
6 * This file is dual-licensed: you can use it either under the terms
46 * SBC-A510 comprises a PCA9555 I2C GPIO expander its GPIO lines connected to
55 * 0.7 mini-PCIe slot W_DISABLE#
67 /dts-v1/;
69 #include "dove-cm-a510.dtsi"
72 model = "Compulab SBC-A510";
73 compatible = "compulab,sbc-a510", "compulab,cm-a510", "marvell,dove";
76 stdout-path = &uart0;
79 usb0_power: regulator-2 {
[all …]
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| H A D | armada-385-db-ap.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * (DB-88F6820-AP)
11 /dts-v1/;
12 #include "armada-385.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
18 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
21 stdout-path = "serial1:115200n8";
36 internal-regs {
38 pinctrl-names = "default";
39 pinctrl-0 = <&i2c0_pins>;
[all …]
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| H A D | armada-370-rd.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (RD-88F6710-A1)
6 * Copied from arch/arm/boot/dts/armada-370-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include <dt-bindings/input/input.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
23 #include <dt-bindings/leds/common.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-370.dtsi"
[all …]
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| H A D | armada-395-gp.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 /dts-v1/;
11 #include "armada-395.dtsi"
15 compatible = "marvell,a395-gp", "marvell,armada395",
19 stdout-path = "serial0:115200n8";
31 internal-regs {
34 clock-frequency = <100000>;
62 clock-frequency = <200000000>;
63 broken-cd;
64 wp-inverted;
[all …]
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| H A D | dove-d3plug.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
20 compatible = "gpio-leds";
21 pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
22 pinctrl-names = "default";
24 led-wlan-act {
25 label = "wlan-act";
29 led-wlan-ap {
30 label = "wlan-ap";
34 led-status {
[all …]
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| H A D | armada-xp-linksys-mamba.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
12 * Based on armada-xp-axpwifiap.dts:
16 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
19 /dts-v1/;
20 #include <dt-bindings/gpio/gpio.h>
21 #include <dt-bindings/input/input.h>
22 #include "armada-xp-mv78230.dtsi"
26 compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
27 "marvell,armadaxp", "marvell,armada-370-xp";
31 stdout-path = &uart0;
[all …]
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| H A D | armada-370-mirabox.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include "armada-370.dtsi"
14 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17 stdout-path = "serial0:115200n8";
30 internal-regs {
35 clock-frequency = <600000000>;
40 compatible = "gpio-leds";
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| H A D | armada-388-clearfog.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include "armada-388.dtsi"
9 #include "armada-38x-solidrun-microsom.dtsi"
13 /* So that mvebu u-boot can update the MAC addresses */
20 stdout-path = "serial0:115200n8";
23 reg_3p3v: regulator-3p3v {
24 compatible = "regulator-fixed";
25 regulator-name = "3P3V";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
[all …]
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/ |
| H A D | PCIeSlot.interface.yaml | 2 This defines a PCIe slot to be exposed for system management. It includes
6 - name: Generation
10 The PCIe generation of the slot
12 - name: Lanes
15 The maximum number of PCIe lanes supported by the slot
17 - name: SlotType
23 - name: HotPluggable
26 Whether this PCIe slot supports hotplug
29 - name: Generations
31 Possible PCIe generations
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| /openbmc/u-boot/board/CZ.NIC/turris_mox/ |
| H A D | turris_mox.c | 1 // SPDX-License-Identifier: GPL-2.0+
40 #define PCIE_PATH "/soc/pcie@d0070000"
46 gd->ram_base = 0; in dram_init()
47 gd->ram_size = (phys_size_t)get_ram_size(0, 0x40000000); in dram_init()
54 gd->bd->bi_dram[0].start = (phys_addr_t)0; in dram_init_banksize()
55 gd->bd->bi_dram[0].size = gd->ram_size; in dram_init_banksize()
69 * if pcie should be enabled in U-Boot's device tree. Therefore we have in board_fix_fdt()
107 printf("Cannot find PCIe node in U-Boot's device tree!\n"); in board_fix_fdt()
113 printf("Cannot %s PCIe in U-Boot's device tree!\n", in board_fix_fdt()
146 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
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| /openbmc/u-boot/board/intel/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
17 PCIe and some other sensor interfaces.
23 mini-ITX form factor containing the Intel Braswell SoC, which has
24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
25 serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
34 peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
43 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
50 eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
56 Arduino-certified development and prototyping boards based on Intel
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | hisilicon,kirin-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin SoCs PCIe host DT description
10 - Xiaowei Song <songxiaowei@hisilicon.com>
11 - Binghui Wang <wangbinghui@hisilicon.com>
14 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15 It shares common functions with the PCIe DesignWare core driver and
17 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
[all …]
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/ |
| H A D | PCIeSlots.v1_6_1.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
36 "description": "The available OEM-specific actions for this resource.",
37 …"longDescription": "This type shall contain the available OEM-specific actions for this resource.",
39 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
58 …"longDescription": "This Redfish Specification-described type shall contain links to resources tha…
60 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
[all …]
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/ |
| H A D | PCIeSlots.v1_6_1.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
36 "description": "The available OEM-specific actions for this resource.",
37 …"longDescription": "This type shall contain the available OEM-specific actions for this resource.",
39 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
58 …"longDescription": "This Redfish Specification-described type shall contain links to resources tha…
60 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
[all …]
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| /openbmc/linux/drivers/media/pci/solo6x10/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Bluecherry / Softlogic 6x10 capture cards (MPEG-4/H.264)"
13 This driver supports the Bluecherry H.264 and MPEG-4 hardware
14 compression capture cards and other Softlogic-based ones.
17 * Bluecherry BC-H16480A (PCIe, 16 port, H.264)
18 * Bluecherry BC-H04120A (PCIe, 4 port, H.264)
19 * Bluecherry BC-H04120A-MPCI (Mini-PCI, 4 port, H.264)
20 * Bluecherry BC-04120A (PCIe, 4 port, MPEG-4)
|
| /openbmc/linux/arch/powerpc/boot/dts/fsl/ |
| H A D | t104xd4rdb.dtsi | 36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
41 bman_fbpr: bman-fbpr {
45 qman_fqd: qman-fqd {
49 qman_pfdr: qman-pfdr {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
66 bank-width = <2>;
[all …]
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| /openbmc/bmcweb/redfish-core/include/utils/ |
| H A D | pcie_util.hpp | 1 // SPDX-License-Identifier: Apache-2.0
2 // SPDX-FileCopyrightText: Copyright OpenBMC Authors
29 * @brief Populate the PCIe Device list from a GetSubTreePaths search of
33 * @param[i] Name Key to store the list of PCIe devices in asyncResp
71 "xyz.openbmc_project.Inventory.Item.PCIeSlot.SlotTypes.Mini") in dbusSlotTypeToRf()
73 return pcie_slots::SlotTypes::Mini; in dbusSlotTypeToRf()
|
| /openbmc/linux/drivers/media/pci/ddbridge/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
20 - Octopus PCIe Bridge
21 - Octopus mini PCIe Bridge
22 - Octopus LE
23 - DuoFlex S2 Octopus
24 - DuoFlex CT Octopus
25 - cineS2(v6)
26 - CineCTv6 and DuoFlex CT (STV0367-based)
27 - CineCTv7 and DuoFlex CT2/C2T2/C2T2I (Sony CXD28xx-based)
28 - MaxA8 series
[all …]
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| /openbmc/u-boot/board/freescale/t104xrdb/ |
| H A D | README | 2 --------
9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
16 The board is re-designed T1040RDB board with following changes :
17 - Support of DDR4 memory and some enhancements
20 The board is re-designed T1040RDB board with following changes :
21 - Support of DDR4 memory
22 - Support for 0x86 serdes protocol which can support following interfaces
23 - 2 RGMII's on DTSEC4, DTSEC5
24 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
27 -------------------------------------------------------------------------
[all …]
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| /openbmc/u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | README | 2 --------
4 P1020MSBG-PC
5 P1020RDB-PC
6 P1020RDB-PD
7 P1020UTM-PC
8 P1021RDB-PC
11 P2020RDB-PC
13 They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
14 has 64-bit DDR. All others have 32-bit DDR.
23 * PCIE slot and mini-PCIE slots
[all …]
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| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 5 The P1010 is a cost-effective, low-power, highly integrated host processor
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
18 - 16 Mbyte SPI memory
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
22 - PCIe:
23 - Lane0: x1 mini-PCIe slot
[all …]
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| /openbmc/linux/drivers/net/can/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 to 8Mbit/s for the more recent CAN with Flexible Data-Rate
11 (CAN-FD). The CAN bus was originally mainly for automotive, but is now
16 This section contains all the CAN(-FD) device drivers including the
21 can-dev.
62 can-dev module.
70 bool "CAN bit-timing calculation"
73 If enabled, CAN bit-timing parameters will be calculated for the
74 bit-rate specified via Netlink argument "bitrate" when the device
76 with standard bit-rates but may fail for exotic bit-rates or CAN
[all …]
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| /openbmc/u-boot/board/freescale/c29xpcie/ |
| H A D | README | 3 C29XPCIE board is a series of Freescale PCIe add-in cards to perform
6 The Freescale C29x family is a high performance crypto co-processor.
12 - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
13 - 64 Mbyte NOR flash single-chip memory
14 - 4 Gbyte NAND flash memory
15 - 1 Mbit AT24C1024 I2C EEPROM
16 - 16 Mbyte SPI memory
19 - 10/100/1000 BaseT Ethernet ports:
20 - eTSEC1, RGMII: one 10/100/1000 port
21 - eTSEC2, RGMII: one 10/100/1000 port
[all …]
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