| /openbmc/linux/drivers/mtd/maps/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Support non-linear mappings of flash chips"
13 tristate "Flash device in physical memory map"
17 ROM driver code to communicate with chips which are mapped
18 physically into the CPU's memory. You will need to configure
21 with config options or at run-time.
42 This is the physical memory location at which the flash chips
43 are mapped on your particular target board. Refer to the
44 memory map which should hopefully be in the documentation for
54 physical memory map between the chips, this could be larger
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| /openbmc/linux/Documentation/admin-guide/mm/ |
| H A D | pagemap.rst | 12 physical frame each virtual page is mapped to. It contains one 64-bit
16 * Bits 0-54 page frame number (PFN) if present
17 * Bits 0-4 swap type if swapped
18 * Bits 5-54 swap offset if swapped
19 * Bit 55 pte is soft-dirty (see
20 Documentation/admin-guide/mm/soft-dirty.rst)
21 * Bit 56 page exclusively mapped (since 4.2)
22 * Bit 57 pte is uffd-wp write-protected (since 5.13) (see
23 Documentation/admin-guide/mm/userfaultfd.rst)
24 * Bits 58-60 zero
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| H A D | nommu-mmap.rst | 2 No-MMU memory mapping support
5 The kernel has limited support for memory mapping under no-MMU conditions, such
6 as are used in uClinux environments. From the userspace point of view, memory
12 Memory mapping behaviour also involves the way fork(), vfork(), clone() and
16 The behaviour is similar between the MMU and no-MMU cases, but not identical;
21 In the MMU case: VM regions backed by arbitrary pages; copy-on-write
24 In the no-MMU case: VM regions backed by arbitrary contiguous runs of
31 the no-MMU case doesn't support these, behaviour is identical to
39 In the no-MMU case:
41 - If one exists, the kernel will re-use an existing mapping to the
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| /openbmc/linux/Documentation/devicetree/bindings/display/ |
| H A D | st,stih4xx.txt | 3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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| /openbmc/linux/mm/ |
| H A D | zpool.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * zpool memory storage api
7 * This is a common frontend for memory storage pool implementations.
8 * Typically, this is used to store compressed memory.
30 * zpool_register_driver() - register a zpool implementation.
36 atomic_set(&driver->refcount, 0); in zpool_register_driver()
37 list_add(&driver->list, &drivers_head); in zpool_register_driver()
43 * zpool_unregister_driver() - unregister a zpool implementation.
57 refcount = atomic_read(&driver->refcount); in zpool_unregister_driver()
60 ret = -EBUSY; in zpool_unregister_driver()
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| /openbmc/qemu/hw/mem/ |
| H A D | sparse-mem.c | 2 * A sparse memory device. Useful for fuzzing
10 * See the COPYING file in the top-level directory.
14 #include "qemu/error-report.h"
16 #include "hw/qdev-properties.h"
21 #include "hw/mem/sparse-mem.h"
33 GHashTable *mapped; member
48 block = g_hash_table_lookup(s->mapped, (void *)pfn); in sparse_mem_read()
50 assert(offset + size <= sizeof(block->data)); in sparse_mem_read()
51 memcpy(&ret, block->data + offset, size); in sparse_mem_read()
64 if (!g_hash_table_lookup(s->mapped, (void *)pfn) && in sparse_mem_write()
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| /openbmc/linux/drivers/net/ethernet/cavium/liquidio/ |
| H A D | octeon_mem_ops.h | 7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * \brief Host Driver: Routines used to read/write Octeon memory.
27 /** Read a 64-bit value from a BAR1 mapped core memory address.
28 * @param oct - pointer to the octeon device.
29 * @param core_addr - the address to read from.
32 * in which core_addr is mapped.
34 * @return 64-bit value read from Core memory
38 /** Read a 32-bit value from a BAR1 mapped core memory address.
39 * @param oct - pointer to the octeon device.
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| /openbmc/linux/drivers/scsi/lpfc/ |
| H A D | lpfc_mem.c | 4 * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term *
6 * Copyright (C) 2004-2014 Emulex. All rights reserved. *
9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
46 #define LPFC_MEM_POOL_SIZE 64 /* max elem in non-DMA safety pool */
48 #define LPFC_RRQ_POOL_SIZE 256 /* max elements in non-DMA pool */
49 #define LPFC_MBX_POOL_SIZE 256 /* max elements in MBX non-DMA pool */
54 int max_xri = phba->sli4_hba.max_cfg_param.max_xri; in lpfc_mem_alloc_active_rrq_pool_s4()
57 return -ENOMEM; in lpfc_mem_alloc_active_rrq_pool_s4()
58 bytes = ((BITS_PER_LONG - 1 + max_xri) / BITS_PER_LONG) * in lpfc_mem_alloc_active_rrq_pool_s4()
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| /openbmc/linux/Documentation/arch/loongarch/ |
| H A D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
12 instruction set, virtual memory and some other topics of LoongArch.
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
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| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | mmap.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
7 Streaming I/O (Memory Mapping)
14 streaming methods, to determine if the memory mapping flavor is
16 with the memory type set to ``V4L2_MEMORY_MMAP``.
19 between application and driver, the data itself is not copied. Memory
20 mapping is primarily intended to map buffers in device memory into the
21 application's address space. Device memory can be for example the video
22 memory on a graphics card with a video capture add-on. However, being
24 drivers support streaming as well, allocating buffers in DMA-able main
25 memory.
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| H A D | vidioc-reqbufs.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_REQBUFS - Initiate Memory Mapping, User Pointer I/O or DMA buffer I/O
34 This ioctl is used to initiate :ref:`memory mapped <mmap>`,
36 Memory mapped buffers are located in device memory and must be allocated
37 with this ioctl before they can be mapped into the application's address
48 the desired number of buffers, ``memory`` must be set to the requested
53 requested, even zero, when the driver runs out of free memory. A larger
62 buffers. Note that if any buffers are still mapped or exported via DMABUF,
76 .. flat-table:: struct v4l2_requestbuffers
77 :header-rows: 0
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| H A D | func-mmap.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _func-mmap:
13 v4l2-mmap - Map device memory into application address space
18 .. code-block:: c
36 Length of the memory area to map. This must be the same value as
39 single-planar API, and the same value as returned by the driver in
41 the multi-planar API.
44 The ``prot`` argument describes the desired memory protection.
57 #. Device memory accesses (e. g. the memory on a graphics card
59 compared to main memory accesses, or reads may be significantly
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| /openbmc/linux/Documentation/core-api/ |
| H A D | dma-api.rst | 8 of the API (and actual examples), see Documentation/core-api/dma-api-howto.rst.
11 Part II describes extensions for supporting non-consistent memory
13 non-consistent platforms (this is usually only legacy platforms) you
16 Part I - dma_API
17 ----------------
19 To get the dma_API, you must #include <linux/dma-mapping.h>. This
27 Part Ia - Using large DMA-coherent buffers
28 ------------------------------------------
36 Consistent memory is memory for which a write by either the device or
40 devices to read that memory.)
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| /openbmc/phosphor-ipmi-flash/bmc/firmware-handler/ |
| H A D | lpc_nuvoton.cpp | 8 * http://www.apache.org/licenses/LICENSE-2.0
29 #include <memory>
50 mappedFd = sys->open(devmem, O_RDWR | O_SYNC); in open()
51 if (mappedFd == -1) in open()
56 mapped = reinterpret_cast<uint8_t*>(sys->mmap( in open()
58 if (mapped == MAP_FAILED) in open()
60 sys->close(mappedFd); in open()
61 mappedFd = -1; in open()
62 mapped = nullptr; in open()
69 output.mapped = mapped; in open()
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| H A D | lpc_handler.hpp | 7 #include <memory>
15 /* Host LPC address where the chunk is to be mapped. */
18 /* Size of the chunk to be mapped. */
23 * Data Handler for configuration the ASPEED LPC memory region, reading and
32 * @param[in] mapper - pointer to a mapper implementation to use.
52 MemorySet memory = {}; member in ipmi_flash::LpcDataHandler
54 /* Offset in reserved memory at which host data arrives. */
55 /* Size of the chunk of the memory region in use by the host (e.g.
56 * mapped over external block mechanism).
|
| /openbmc/u-boot/arch/sandbox/include/asm/ |
| H A D | u-boot-sandbox.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
30 * pci_map_physmem() - map a PCI device into memory
32 * This is used on sandbox to map a device into memory so that it can be
33 * used with normal memory access. After this call, some part of the device's
38 * @paddr: Physical memory address, normally corresponding to a PCI BAR
40 * to the size actually mapped, which may be less if the device
42 * @devp: Returns the device which mapped into this space
43 * @ptrp: Returns a pointer to the mapped address. The device's space
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| /openbmc/linux/Documentation/userspace-api/media/dvb/ |
| H A D | dmx-reqbufs.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 DMX_REQBUFS - Initiate Memory Mapping and/or DMA buffer I/O
36 This ioctl is used to initiate a memory mapped or DMABUF based demux I/O.
38 Memory mapped buffers are located in device memory and must be allocated
39 with this ioctl before they can be mapped into the application's address
54 … be smaller than the number requested, even zero, when the driver runs out of free memory. A larger
63 buffers, however this cannot succeed when any buffers are still mapped.
70 On success 0 is returned, on error -1 and the ``errno`` variable is set
72 :ref:`Generic Error Codes <gen-errors>` chapter.
|
| H A D | dmx-mmap.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _dmx-mmap:
13 dmx-mmap - Map device memory into application address space
20 .. code-block:: c
38 Length of the memory area to map. This must be a multiple of the
42 The ``prot`` argument describes the desired memory protection.
49 The ``flags`` parameter specifies the type of the mapped object,
50 mapping options and whether modifications made to the mapped copy of
61 ``MAP_SHARED`` allows applications to share the mapped memory with
62 other (e. g. child-) processes.
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| /openbmc/u-boot/arch/x86/cpu/quark/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
29 to the resulting U-Boot image. It is a data block (up to 64K) of
30 machine-specific code which must be put in the flash for the RMU
48 put in flash at a location matching the strap-determined base address.
71 Embedded SRAM (eSRAM) memory-mapped base address.
81 Root Complex register block memory-mapped base address.
87 ACPI Power Management 1 (PM1) i/o-mapped base address.
94 ACPI Processor Block (PBLK) i/o-mapped base address.
101 SPI DMA i/o-mapped base address.
107 GPIO i/o-mapped base address.
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| /openbmc/linux/include/xen/interface/ |
| H A D | memory.h | 1 /* SPDX-License-Identifier: MIT */
3 * memory.h
5 * Memory reservation and information.
16 * Increase or decrease the specified domain's memory reservation. Returns a
17 * -ve errcode on failure, or the # extents successfully allocated or freed.
31 * IN: GPFN bases of extents to populate with memory
43 * I/O devices often have a 32-bit limitation even in 64-bit systems). If
59 * An atomic exchange of memory pages. If return code is zero then
60 * @out.extent_list provides GMFNs of the newly-allocated memory.
68 * [IN] Details of memory extents to be exchanged (GMFN bases).
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| /openbmc/linux/arch/um/kernel/ |
| H A D | physmem.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
12 #include <as-layout.h>
18 static int physmem_fd = -1;
50 if (err == -ENOMEM) in map_memory()
53 "memory size>/4096\n"); in map_memory()
60 * setup_physmem() - Setup physical memory for UML
61 * @start: Start address of the physical kernel memory,
63 * @reserve_end: end address of the physical kernel memory.
64 * @len: Length of total physical memory that should be mapped/made
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| /openbmc/linux/drivers/virtio/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
73 If disabled, you get a slightly smaller, non-transitional driver,
101 This driver provides access to virtio-pmem devices, storage devices
102 that are mapped into the physical address space - similar to NVDIMMs
103 - with a virtio-based flushing interface.
114 of memory within a KVM guest.
127 This driver provides access to virtio-mem paravirtualized memory
128 devices, allowing to hotplug and hotunplug memory.
130 This driver currently only supports x86-64 and arm64. Although it
131 should compile on other architectures that implement memory
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| /openbmc/linux/arch/sh/mm/ |
| H A D | ioremap.c | 5 * (C) Copyright 2005 - 2010 Paul Mundt
7 * Re-map IO memory to kernel address space so that we can access it.
8 * This is needed for high PCI addresses that aren't mapped in the
9 * 640k-1MB IO memory area on PC's
31 * On 32-bit SH, we traditionally have the whole physical address space mapped
42 phys_addr_t last_addr = offset + size - 1; in __ioremap_29bit()
46 * mapped. Uncached access for P1 addresses are done through P2. in __ioremap_29bit()
47 * In the P3 case or for addresses outside of the 29-bit space, in __ioremap_29bit()
65 /* P4 above the store queues are always mapped. */ in __ioremap_29bit()
78 void __iomem *mapped; in ioremap_prot() local
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| /openbmc/qemu/docs/devel/ |
| H A D | memory.rst | 2 The memory API
5 The memory API models the memory and I/O buses and controllers of a QEMU
8 - ordinary RAM
9 - memory-mapped I/O (MMIO)
10 - memory controllers that can dynamically reroute physical memory regions
13 The memory model provides support for
15 - tracking RAM changes by the guest
16 - setting up coalesced memory for kvm
17 - setting up ioeventfd regions for kvm
19 Memory is modelled as an acyclic graph of MemoryRegion objects. Sinks
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| /openbmc/linux/drivers/media/pci/cx18/ |
| H A D | cx18-io.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * cx18 driver PCI memory mapped IO access routines
12 #include "cx18-driver.h"
23 /* Non byteswapping memory mapped IO */
45 /* Normal memory mapped IO */
136 /* Access "register" region of CX23418 memory mapped I/O */
139 cx18_writel_noretry(cx, val, cx->reg_mem + reg); in cx18_write_reg_noretry()
144 cx18_writel(cx, val, cx->reg_mem + reg); in cx18_write_reg()
150 cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask); in cx18_write_reg_expect()
155 return cx18_readl(cx, cx->reg_mem + reg); in cx18_read_reg()
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