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/openbmc/linux/Documentation/arch/ia64/
H A Dmca.rst2 An ad-hoc collection of notes on IA64 MCA and INIT processing
9 MCA/INIT are completely asynchronous. They can occur at any time, when
11 holding a spinlock. Trying to get any lock from MCA/INIT state is
17 The complicated ia64 MCA process. All of this is mandated by Intel's
21 * MCA occurs on one cpu, usually due to a double bit memory error.
24 * SAL sends an MCA rendezvous interrupt (which is a normal interrupt)
27 * Slave cpus that receive the MCA interrupt call down into SAL, they
28 end up spinning disabled while the MCA is being serviced.
30 * If any slave cpu was already spinning disabled when the MCA occurred
31 then it cannot service the MCA interrupt. SAL waits ~20 seconds then
[all …]
/openbmc/linux/sound/soc/apple/
H A Dmca.c3 // Apple SoCs MCA driver
7 // The MCA peripheral is made up of a number of identical units called clusters.
181 struct mca_data *mca = snd_soc_dai_get_drvdata(dai); in mca_dai_to_cluster() local
186 int cluster_no = dai->id % mca->nclusters; in mca_dai_to_cluster()
188 return &mca->clusters[cluster_no]; in mca_dai_to_cluster()
261 struct mca_data *mca = cl->host; in mca_fe_enable_clocks() local
266 dev_err(mca->dev, in mca_fe_enable_clocks()
277 cl->pd_link = device_link_add(mca->dev, cl->pd_dev, in mca_fe_enable_clocks()
281 dev_err(mca->dev, in mca_fe_enable_clocks()
306 struct mca_data *mca = cl->host; in mca_fe_clocks_in_use() local
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H A DMakefile1 snd-soc-apple-mca-objs := mca.o
3 obj-$(CONFIG_SND_SOC_APPLE_MCA) += snd-soc-apple-mca.o
H A DKconfig2 tristate "Apple Silicon MCA driver"
7 This option enables an ASoC platform driver for MCA peripherals found
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mca.c79 if (!adev->mca.mp0.ras) in amdgpu_mca_mp0_ras_sw_init()
82 ras = adev->mca.mp0.ras; in amdgpu_mca_mp0_ras_sw_init()
86 dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n"); in amdgpu_mca_mp0_ras_sw_init()
90 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); in amdgpu_mca_mp0_ras_sw_init()
93 adev->mca.mp0.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp0_ras_sw_init()
103 if (!adev->mca.mp1.ras) in amdgpu_mca_mp1_ras_sw_init()
106 ras = adev->mca.mp1.ras; in amdgpu_mca_mp1_ras_sw_init()
110 dev_err(adev->dev, "Failed to register mca.mp1 ras block!\n"); in amdgpu_mca_mp1_ras_sw_init()
114 strcpy(ras->ras_block.ras_comm.name, "mca.mp1"); in amdgpu_mca_mp1_ras_sw_init()
117 adev->mca.mp1.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp1_ras_sw_init()
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/openbmc/linux/drivers/infiniband/sw/rxe/
H A Drxe_mcast.c11 * struct rxe_mca ('mca'). An mcg is allocated each time a qp is
17 * mca is created. It holds a pointer to the qp and is added to a list
284 * __rxe_init_mca - initialize a new mca holding lock
287 * @mca: empty space for new mca
290 * and pass memory for new mca
295 struct rxe_mca *mca) in __rxe_init_mca() argument
316 mca->qp = qp; in __rxe_init_mca()
318 list_add_tail(&mca->qp_list, &mcg->qp_list); in __rxe_init_mca()
334 struct rxe_mca *mca, *tmp; in rxe_attach_mcg() local
339 list_for_each_entry(mca, &mcg->qp_list, qp_list) { in rxe_attach_mcg()
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H A Drxe_recv.c194 struct rxe_mca *mca; in rxe_rcv_mcast_pkt() local
217 list_for_each_entry(mca, &mcg->qp_list, qp_list) { in rxe_rcv_mcast_pkt()
218 qp = mca->qp; in rxe_rcv_mcast_pkt()
233 if (mca->qp_list.next != &mcg->qp_list) { in rxe_rcv_mcast_pkt()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dapple,mca.yaml4 $id: http://devicetree.org/schemas/sound/apple,mca.yaml#
7 title: Apple MCA I2S transceiver
10 MCA is an I2S transceiver peripheral found on M1 and other Apple chips. It is
12 or in an interlinked fashion. Up to 6 clusters have been seen on an MCA.
24 - apple,t6000-mca
25 - apple,t8103-mca
26 - apple,t8112-mca
27 - const: apple,mca
31 - description: Register region of the MCA clusters proper
117 mca: i2s@9b600000 {
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/openbmc/linux/arch/ia64/kernel/
H A Dmca.c3 * File: mca.c
4 * Purpose: Generic MCA handling layer
28 * Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38 * Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
54 * Avoid deadlock when using printk() for MCA and INIT records.
61 * Convert MCA/INIT handlers to use per event stacks and SAL/OS
68 * Add printing support for MCA/INIT.
99 #include <asm/mca.h>
126 if ((notify_die((event), "MCA", (regs), (arg), 0, 0) \
176 * limited & delayed printing support for MCA/INIT handler
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H A Dmca_asm.S4 * Purpose: assembly portion of the IA64 MCA handling
22 * Added per cpu MCA/INIT stack save areas.
25 * Use per cpu MCA/INIT stacks for all data.
33 #include <asm/mca.h>
142 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
144 mov r19=1 // All MCA events are treated as monarch (for now)
149 // Using MCA stack, struct ia64_sal_os_state, variable proc_state_param
234 // switch to per cpu MCA stack
235 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
241 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
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H A Dmca_drv.c4 * Purpose: Generic MCA handling layer
32 #include <asm/mca.h>
86 ia64_mca_printk(KERN_ALERT "MCA: %s\n", buf); in fatal_mca()
100 ia64_mca_printk(KERN_INFO "MCA: %s\n", buf); in mca_recovered()
152 * @paddr: poisoned address received from MCA Handler
160 "iip: %p, psr: 0x%lx,paddr: 0x%lx](%s) encounters MCA.\n", in mca_handler_bh()
331 * MCA handler cannot allocate new memory on flight, in init_record_index_pools()
365 * is_mca_global - Check whether this MCA is global or not
382 * PAL can request a rendezvous, if the MCA has a global scope. in is_mca_global()
383 * If "rz_always" flag is set, SAL requests MCA rendezvous in is_mca_global()
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H A Dsalinfo.c22 * Periodically check for outstanding MCA or INIT records.
28 * mca.c may not pass a buffer, a NULL buffer just indicates that a new
78 "mca",
86 ARRAY_SIZE(salinfo_log_name) + /* /proc/sal/{mca,...} */
87 (2 * ARRAY_SIZE(salinfo_log_name)) + /* /proc/sal/mca/{event,data} */
91 * that are owned by mca.c.
120 * read data -> return the INIT/MCA/CMC/CPE record.
154 struct salinfo_data_saved data_saved[5];/* save last 5 records from mca.c, must be < 255 */
200 /* This routine is invoked in interrupt context. Note: mca.c enables
201 * interrupts before calling this code for CMC/CPE. MCA and INIT events are
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H A Dcrash.c23 #include <asm/mca.h>
97 ia64_set_psr_mc(); /* mask MCA/INIT */ in machine_crash_shutdown()
147 ia64_set_psr_mc(); /* mask MCA/INIT and stop reentrance */ in kdump_cpu_freeze()
208 /* *(nd->data) indicate if MCA is recoverable */ in kdump_init_notifier()
212 /* We got fatal MCA while kdump!? No way!! */ in kdump_init_notifier()
H A Dmca_drv.h4 * Purpose: Define helpers for Generic MCA handling
116 int start_addr; /* location-relative starting address of MCA recoverable range */
117 int end_addr; /* location-relative ending address of MCA recoverable range */
/openbmc/linux/arch/ia64/include/asm/
H A Dmca.h3 * File: mca.h
64 /* Handover state from SAL to OS and vice versa, for both MCA and INIT events.
76 unsigned long rv_rc; /* MCA - Rendezvous state, INIT - reason code */
85 * Note: if the MCA/INIT recovery code wants to resume to a new context
92 * switch_stack. Because MCA/INIT can occur when interrupts are
94 * MCA/INIT and resume.
131 /* Per-CPU MCA state that is too big for normal per-CPU variables. */
138 /* Array of physical addresses of each CPU's MCA area. */
H A Dmca_asm.h216 * The MCA and INIT stacks in struct ia64_mca_cpu look like normal kernel
218 * top of the MCA/INIT stack. To support concurrent entry to MCA or INIT, as
219 * well as MCA over INIT, each event needs its own SAL/OS state. All entries
230 * +---------------------------+ <-------- SP at start of C MCA handler
233 * | RBS for MCA/INIT handler |
235 * | struct task for MCA/INIT |
236 * +---------------------------+ <-------- Bottom of MCA/INIT stack
/openbmc/linux/arch/x86/kernel/cpu/mce/
H A Dinternal.h153 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
154 * the register space for each MCA bank and also increases number of
155 * banks. Also, to accommodate the new banks and registers, the MCA
166 /* Pentium, family 5-style MCA */
169 /* Centaur Winchip C6-style MCA */
H A Damd.c53 /* Scalable MCA: */
166 /* ZN Core (HWID=0xB0) MCA types */
177 /* Data Fabric MCA types */
182 /* Unified Memory Controller MCA type */
186 /* Parameter Block MCA type */
189 /* Platform Security Processor MCA type */
193 /* System Management Unit MCA type */
197 /* Microprocessor 5 Unit MCA type */
200 /* MPDMA MCA type */
203 /* Northbridge IO Unit MCA type */
[all …]
H A Dseverity.c86 PANIC, "MCIP not set in MCA handler",
343 * On MCA overflow, without the MCA overflow recovery feature the in mce_severity_amd()
347 panic_msg = "Overflowed uncorrected error without MCA Overflow Recovery"; in mce_severity_amd()
353 panic_msg = "Uncorrected error without MCA Recovery"; in mce_severity_amd()
/openbmc/linux/net/packet/
H A Ddiag.c40 struct nlattr *mca; in pdiag_put_mclist() local
43 mca = nla_nest_start_noflag(nlskb, PACKET_DIAG_MCLIST); in pdiag_put_mclist()
44 if (!mca) in pdiag_put_mclist()
54 nla_nest_cancel(nlskb, mca); in pdiag_put_mclist()
67 nla_nest_end(nlskb, mca); in pdiag_put_mclist()
/openbmc/linux/arch/x86/include/asm/
H A Dmce.h19 #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
55 * McaX field if set indicates a given bank supports MCA extensions:
73 #define MCACOD 0xefff /* MCA Error Code */
112 /* AMD Scalable MCA */
226 /* Maximum number of MCA banks per CPU. */
268 /* Disable CMCI/polling for MCA bank claimed by firmware */
294 * Scalable MCA.
H A Dmpspec_def.h88 #define BUSTYPE_MCA "MCA" /* Obsolete */
171 * 4 2 CPU MCA 82489DX
174 * 7 2 CPU MCA+PCI
H A Damd_nb.h34 unsigned int bank; /* MCA bank the block belongs to */
35 unsigned int cpu; /* CPU which controls MCA bank */
/openbmc/linux/include/xen/interface/
H A Dxen-mca.h3 * arch-x86/mca.h
59 * mca machine check info are recorded in mc_info entries.
60 * when fetch mca info, it can use MC_TYPE_... to distinguish
61 * different mca info.
/openbmc/openbmc-test-automation/openpower/ras/
H A Dras_utils.robot51 ... (e.g: Processor core, CAPP, MCA) through BMC/HOST.
79 ... (e.g: Processor core, CAPP, MCA) through BMC/HOST.
210 ... (e.g: Processor core, CAPP, MCA) through BMC using

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