arch/ia64/mca.rst

2 An ad-hoc collection of notes on IA64 MCA and INIT processing
9 MCA/INIT are completely asynchronous.  They can occur at any time, when
11 holding a spinlock.  Trying to get any lock from MCA/INIT state is
17 The complicated ia64 MCA process.  All of this is mandated by Intel's
21 * MCA occurs on one cpu, usually due to a double bit memory error.
24 * SAL sends an MCA rendezvous interrupt (which is a normal interrupt)
27 * Slave cpus that receive the MCA interrupt call down into SAL, they
28   end up spinning disabled while the MCA is being serviced.
30 * If any slave cpu was already spinning disabled when the MCA occurred
31   then it cannot service the MCA interrupt.  SAL waits ~20 seconds then
35 * Because MCA/INIT can be delivered at any time, including when the cpu
37   event are _completely_ undefined.  In particular the MCA/INIT
40   TP on return.  However MCA/INIT events expose us to these PAL
43 * If an MCA/INIT event occurs while the kernel was running (not user
44   space) and the kernel has called PAL then the MCA/INIT handler cannot
47   Because the MCA/INIT handlers cannot trust the kernel stack, they
48   have to use their own, per-cpu stacks.  The MCA/INIT stacks are
69   knows how to start unwinding it.  The tasks that received an MCA or
71   tasks.  But (and its a big but), the cpus that received the MCA
76   switches to an MCA/INIT stack, registers its new stack using
81 * MCA/INIT can be nested, to a depth of 2 on any cpu.  In the case of a
82   nested error, we want diagnostics on the MCA/INIT handler that
84   requires set_curr_task() so the MCA/INIT handlers can register their
90     struct task and the kernel stacks.  Then the MCA/INIT data would be
95     stacks meant separate "tasks" for the MCA/INIT handlers.
99 INIT is less complicated than MCA.  Pressing the nmi button or using
117 violations.  Unfortunately MCA/INIT start off as massive layer
127 How is ia64 MCA/INIT different from x86 NMI?
129 * x86 NMI typically gets delivered to one cpu.  MCA/INIT gets sent to
132 * x86 NMI cannot be nested.  MCA/INIT can be nested, to a depth of 2
140   about any registers having changed.  MCA/INIT can occur while the cpu
150 What happens when MCA/INIT is delivered what a cpu is running user
153 The user mode registers are stored in the RSE area of the MCA/INIT on
155 mode registers are preserved across a recoverable MCA/INIT.  Since the
157 MCA/INIT never tries to backtrace user space.  Which means that the OS
166 How do we get a backtrace on the tasks that were running when MCA/INIT
169 mca.c:::ia64_mca_modify_original_stack().  That identifies and
171 the MCA/INIT stack's RSE to the original stack's RSE, copies the
181 How do we identify the tasks that were running when MCA/INIT was
185 state, then sos->prev_task on the MCA/INIT stack is updated to point to
190 The sos data is always in the MCA/INIT handler stack, at offset
195 Also the comm field of the MCA/INIT task is modified to include the pid
197 'MCA 12159' means that pid 12159 was running when the MCA was