| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | iommu.txt | 49 association of masters to be configured. Note that an IOMMU can by design
56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
70 Devices that access memory through an IOMMU are called masters. A device can
91 - pasid-num-bits: Some masters support multiple address spaces for DMA, by
105 Firmware has to opt-in stalling, because most buses and masters don't
108 won't work in systems and masters that haven't been designed for
146 * Masters are statically associated with this IOMMU and share
148 * have sufficient information to distinguish between masters.
151 * all masters at any given point in time.
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| /openbmc/linux/Documentation/trace/ |
| H A D | stm.rst | 11 these masters and channels are statically allocated to certain
23 master 7 channel 15, while arbitrary user applications can use masters
28 identifiers to ranges of masters and channels. If these rules (policy)
33 have a name (string identifier) and a range of masters and channels
41 channels masters
42 $ cat /config/stp-policy/dummy_stm.my-policy/user/masters
48 masters 48 through 63 and channel allocation pool has channels 0
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| /openbmc/linux/drivers/staging/vme_user/ |
| H A D | vme_fake.c | 65 struct fake_master_window masters[FAKE_MAX_MASTER]; member
317 bridge->masters[i].enabled = enabled; in fake_master_set()
318 bridge->masters[i].vme_base = vme_base; in fake_master_set()
319 bridge->masters[i].size = size; in fake_master_set()
320 bridge->masters[i].aspace = aspace; in fake_master_set()
321 bridge->masters[i].cycle = cycle; in fake_master_set()
322 bridge->masters[i].dwidth = dwidth; in fake_master_set()
348 *enabled = bridge->masters[i].enabled; in __fake_master_get()
349 *vme_base = bridge->masters[i].vme_base; in __fake_master_get()
350 *size = bridge->masters[i].size; in __fake_master_get()
[all …]
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| /openbmc/openpower-proc-control/procedures/phal/ |
| H A D | set_SPI_mux.cpp | 31 * Sets the mux on the P10 to the FSI SPI masters rather than the PIB SPI
32 * masters. This should only be executed before the host is powering on since
33 * the host will set the mux to the PIB SPI masters.
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | dma-router.yaml | 25 dma-masters:
39 - dma-masters
51 dma-masters = <&sdma>;
|
| H A D | snps,dw-axi-dmac.yaml | 65 snps,dma-masters:
67 Number of AXI masters supported by the hardware.
109 - snps,dma-masters
149 snps,dma-masters = <2>;
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| H A D | st,stm32-dmamux.yaml | 34 - dma-masters
49 dma-masters = <&dma1>, <&dma2>;
|
| H A D | renesas,rzn1-dmamux.yaml | 30 dma-masters:
49 dma-masters = <&dma0 &dma1>;
|
| H A D | lpc1850-dmamux.txt | 12 - dma-masters: phandle pointing to the DMA controller
41 dma-masters = <&dmac>;
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| H A D | snps,dma-spear1340.yaml | 62 dma-masters:
65 Number of DMA masters supported by the controller. In case if
175 dma-masters = <4>;
|
| /openbmc/phosphor-mrw-tools/ |
| H A D | gen_callouts.pl | 58 my %masters;
66 push(@{$masters{$port}}, $slave);
69 for my $m (keys %masters)
71 for my $s(@{$masters{$m}})
|
| /openbmc/linux/drivers/fsi/ |
| H A D | fsi-master.h | 4 * to allow the core to interact with the (hardware-specific) masters.
18 * These are used by hardware masters, such as the one in the FSP2, AST2600 and
59 #define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */
77 * These are used by low level masters that bit-bang out the protocol
118 * These are common to all masters
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/ |
| H A D | metrics.json | 3 "BriefDescription": "bytes all masters read from ddr based on read-cycles event",
11 "BriefDescription": "bytes all masters write to ddr based on write-cycles event",
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mn/sys/ |
| H A D | metrics.json | 3 "BriefDescription": "bytes all masters read from ddr based on read-cycles event",
11 "BriefDescription": "bytes all masters write to ddr based on write-cycles event",
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ |
| H A D | metrics.json | 3 "BriefDescription": "bytes all masters read from ddr based on read-cycles event",
11 "BriefDescription": "bytes all masters write to ddr based on write-cycles event",
|
| /openbmc/linux/Documentation/devicetree/bindings/fsi/ |
| H A D | fsi.txt | 11 FSI masters may require their own DT nodes (to describe the master HW itself);
15 Under the masters' nodes, we can describe the bus topology using nodes to
43 FSI masters
62 masters that may be present on the bus.
|
| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-stm | 1 What: /sys/class/stm/<stm>/masters
24 assigned masters.
|
| H A D | configfs-stp-policy | 34 What: /config/stp-policy/<device>.<policy>/<node>/masters
38 Range of masters from which to allocate for users of this node.
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | cci-control-port.yaml | 7 title: CCI Interconnect Bus Masters
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
|
| /openbmc/linux/drivers/soundwire/ |
| H A D | intel_bus_common.c | 80 * case if one or more masters remain active. In this condition, in intel_start_bus_after_reset()
81 * all the masters are powered on for they are in the same power in intel_start_bus_after_reset()
265 * all the Masters in the steam with the expectation that in intel_post_bank_switch()
267 * and do nothing for the other Masters in intel_post_bank_switch()
|
| /openbmc/linux/drivers/i2c/muxes/ |
| H A D | i2c-mux-pca9541.c | 29 * The PCA9541 is a bus master selector. It supports two I2C masters connected
38 * This driver assumes that the two bus masters are controlled by two different
39 * hosts. If a single host controls both masters, platform code has to ensure
40 * that only one of the masters is instantiated at any given time.
158 * The main contention point occurs if the slave bus is off and both masters
|
| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91sam9263_matrix.h | 18 * 16 masters and 16 slaves.
19 * Note: not all masters/slaves are available
|
| H A D | at91sam9260_matrix.h | 18 * 16 masters and 16 slaves.
20 * 6 Masters and 5 Slaves!
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | brcm,gisb-arb.yaml | 40 32-bits wide bitmask used to specify which GISB masters are valid at the
46 String list of the literal name of the GISB masters. Should match the
|
| /openbmc/linux/drivers/dma/ |
| H A D | stm32-dmamux.c | 48 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
49 * [0] holds number of DMA Masters.
133 dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1); in stm32_dmamux_route_allocate()
192 count = device_property_count_u32(&pdev->dev, "dma-masters"); in stm32_dmamux_probe()
205 dma_node = of_parse_phandle(node, "dma-masters", i - 1); in stm32_dmamux_probe()
|