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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_cp110.c71 u32 mask, unsigned long usec_timout) in polling_with_timeout() argument
77 data = readl(addr) & mask; in polling_with_timeout()
90 u32 mask, data, ret = 1; in comphy_pcie_power_up() local
137 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_pcie_power_up()
139 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_pcie_power_up()
141 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_pcie_power_up()
143 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_pcie_power_up()
145 mask |= COMMON_PHY_PHY_MODE_MASK; in comphy_pcie_power_up()
147 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
150 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_pcie_power_up()
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dat91_gpio.c48 u32 mask; in at91_set_port_pullup() local
50 mask = 1 << offset; in at91_set_port_pullup()
52 writel(mask, &at91_port->puer); in at91_set_port_pullup()
54 writel(mask, &at91_port->pudr); in at91_set_port_pullup()
55 writel(mask, &at91_port->per); in at91_set_port_pullup()
74 u32 mask; in at91_set_pio_periph() local
77 mask = 1 << pin; in at91_set_pio_periph()
78 writel(mask, &at91_port->idr); in at91_set_pio_periph()
80 writel(mask, &at91_port->per); in at91_set_pio_periph()
92 u32 mask; in at91_set_a_periph() local
[all …]
H A Dlpc32xx_gpio.c69 int port, mask; in lpc32xx_gpio_direction_input() local
74 mask = GPIO_TO_MASK(offset); in lpc32xx_gpio_direction_input()
78 writel(mask, &regs->p0_dir_clr); in lpc32xx_gpio_direction_input()
81 writel(mask, &regs->p1_dir_clr); in lpc32xx_gpio_direction_input()
85 writel(mask, &regs->p2_p3_dir_clr); in lpc32xx_gpio_direction_input()
89 if ((mask >= 25) && (mask <= 30)) in lpc32xx_gpio_direction_input()
90 writel(mask, &regs->p2_p3_dir_clr); in lpc32xx_gpio_direction_input()
111 int port, rank, mask, value; in lpc32xx_gpio_get_value() local
140 mask = GPIO_TO_MASK(offset); in lpc32xx_gpio_get_value()
142 return (value & mask) >> rank; in lpc32xx_gpio_get_value()
[all …]
H A Datmel_pio4.c49 u32 reg, mask; in atmel_pio4_config_io_func() local
58 mask = 1 << pin; in atmel_pio4_config_io_func()
62 writel(mask, &port_base->mskr); in atmel_pio4_config_io_func()
127 u32 reg, mask; in atmel_pio4_set_pio_output() local
136 mask = 0x01 << pin; in atmel_pio4_set_pio_output()
139 writel(mask, &port_base->mskr); in atmel_pio4_set_pio_output()
143 writel(mask, &port_base->sodr); in atmel_pio4_set_pio_output()
145 writel(mask, &port_base->codr); in atmel_pio4_set_pio_output()
153 u32 reg, mask; in atmel_pio4_get_pio_input() local
162 mask = 0x01 << pin; in atmel_pio4_get_pio_input()
[all …]
/openbmc/u-boot/drivers/pinctrl/
H A Dpinctrl-at91.c82 void (*mux_A_periph)(struct at91_port *pio, u32 mask);
83 void (*mux_B_periph)(struct at91_port *pio, u32 mask);
84 void (*mux_C_periph)(struct at91_port *pio, u32 mask);
85 void (*mux_D_periph)(struct at91_port *pio, u32 mask);
86 void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
87 void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
89 void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
90 void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
103 static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask) in at91_mux_disable_interrupt() argument
105 writel(mask, &pio->idr); in at91_mux_disable_interrupt()
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zc702/
H A Dps7_init_gpl.c21 // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
29 // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
32 // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
35 // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
41 // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
48 // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
55 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
62 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
69 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
76 // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zc706/
H A Dps7_init_gpl.c21 // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
29 // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
32 // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
35 // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
41 // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
48 // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
55 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
62 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
69 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
76 // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
[all …]
/openbmc/u-boot/arch/microblaze/include/asm/
H A Dbitops.h39 int mask; in set_bit() local
43 mask = 1 << (nr & 0x1f); in set_bit()
45 *a |= mask; in set_bit()
52 int mask; in __set_bit() local
55 mask = 1 << (nr & 0x1f); in __set_bit()
56 *a |= mask; in __set_bit()
69 int mask; in clear_bit() local
73 mask = 1 << (nr & 0x1f); in clear_bit()
75 *a &= ~mask; in clear_bit()
84 int mask; in change_bit() local
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-microzed/
H A Dps7_init_gpl.c21 // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
29 // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
32 // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
35 // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
41 // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
48 // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
55 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
62 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
69 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
76 // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zed/
H A Dps7_init_gpl.c21 // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
29 // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
32 // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
35 // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
41 // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
48 // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
55 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
62 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
69 // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
76 // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zybo/
H A Dps7_init_gpl.c13 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
21 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
24 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
27 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
33 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
40 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
47 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
54 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
61 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
68 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386-bmi2.c45 insn2q(pext, src, "r", mask, "rm")
46 insn2q(pdep, src, "r", mask, "rm")
58 insn2l(pext, src, "r", mask, "rm") in insn1q()
59 insn2l(pdep, src, "r", mask, "rm") in insn1q()
73 uint64_t mask = 0xa080800302020001ull; in insn1q() local
78 result = andnq(mask, ehlo); in insn1q()
81 result = pextq(ehlo, mask); in insn1q()
84 result = pdepq(result, mask); in insn1q()
85 assert(result == (ehlo & mask)); in insn1q()
87 result = pextq(-1ull, mask); in insn1q()
[all …]
/openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/python3-inotify/
H A Dnew-test-inotify.patch69 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=256, cookie=0, len=16), ['IN_CREATE'],…
70 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=32, cookie=0, len=16), ['IN_OPEN'], in…
71 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=8, cookie=0, len=16), ['IN_CLOSE_WRITE…
72 + (inotify.adapters._INOTIFY_EVENT(wd=wd, mask=256, cookie=0, len=16), ['IN_CREATE']…
73 + (inotify.adapters._INOTIFY_EVENT(wd=wd, mask=32, cookie=0, len=16), ['IN_OPEN'], i…
74 + (inotify.adapters._INOTIFY_EVENT(wd=wd, mask=8, cookie=0, len=16), ['IN_CLOSE_WRIT…
110 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=256, cookie=0, len=16), ['IN_CREATE'],…
111 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=32, cookie=0, len=16), ['IN_OPEN'], in…
112 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=8, cookie=0, len=16), ['IN_CLOSE_WRITE…
113 + (inotify.adapters._INOTIFY_EVENT(wd=wd, mask=256, cookie=0, len=16), ['IN_CREATE']…
[all …]
/openbmc/u-boot/include/
H A Dbitfield.h25 * mask = bitfield_mask(10, 5);
31 * mask = bitfield_mask(10, 5);
32 * old = bitfield_extract_by_mask(old_reg_val, mask);
33 * new_reg_val = bitfield_replace_by_mask(old_reg_val, mask, new);
41 /* Produces a mask of set bits covering a range of a uint value */
60 uint mask = bitfield_mask(shift, width); in bitfield_replace() local
62 return (reg_val & ~mask) | ((bitfield_val << shift) & mask); in bitfield_replace()
65 /* Produces a shift of the bitfield given a mask */
66 static inline uint bitfield_shift(uint mask) in bitfield_shift() argument
68 return mask ? ffs(mask) - 1 : 0; in bitfield_shift()
[all …]
/openbmc/u-boot/arch/sh/include/asm/
H A Dbitops.h16 int mask; in set_bit() local
21 mask = 1 << (nr & 0x1f); in set_bit()
23 *a |= mask; in set_bit()
34 int mask; in clear_bit() local
39 mask = 1 << (nr & 0x1f); in clear_bit()
41 *a &= ~mask; in clear_bit()
47 int mask; in change_bit() local
52 mask = 1 << (nr & 0x1f); in change_bit()
54 *a ^= mask; in change_bit()
60 int mask, retval; in test_and_set_bit() local
[all …]
/openbmc/u-boot/drivers/misc/
H A Dgpio_led.c18 static int gpio_led_gpio_value(led_id_t mask, int state) in gpio_led_gpio_value() argument
23 if (gpio_led_inv[i] == mask) in gpio_led_gpio_value()
30 void __led_init(led_id_t mask, int state) in __led_init() argument
34 if (gpio_request(mask, "gpio_led") != 0) { in __led_init()
35 printf("%s: failed requesting GPIO%lu!\n", __func__, mask); in __led_init()
39 gpio_value = gpio_led_gpio_value(mask, state); in __led_init()
40 gpio_direction_output(mask, gpio_value); in __led_init()
43 void __led_set(led_id_t mask, int state) in __led_set() argument
45 int gpio_value = gpio_led_gpio_value(mask, state); in __led_set()
47 gpio_set_value(mask, gpio_value); in __led_set()
[all …]
/openbmc/u-boot/arch/riscv/include/asm/
H A Dbitops.h38 int mask; in __set_bit() local
41 mask = 1 << (nr & 0x1f); in __set_bit()
42 *a |= mask; in __set_bit()
50 int mask; in __clear_bit() local
53 mask = 1 << (nr & 0x1f); in __clear_bit()
54 *a &= ~mask; in __clear_bit()
61 int mask; in __change_bit() local
65 mask = 1 << (nr & 31); in __change_bit()
66 *ADDR ^= mask; in __change_bit()
71 int mask, retval; in __test_and_set_bit() local
[all …]
/openbmc/u-boot/cmd/x86/
H A Dmtrr.c25 "Mask ||", "Size ||"); in do_mtrr_list()
28 uint64_t base, mask, size; in do_mtrr_list() local
32 mask = native_read_msr(MTRR_PHYS_MASK_MSR(i)); in do_mtrr_list()
33 size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); in do_mtrr_list()
36 valid = mask & MTRR_PHYS_MASK_VALID; in do_mtrr_list()
40 mask & ~MTRR_PHYS_MASK_VALID, size); in do_mtrr_list()
51 uint64_t base, mask; in do_mtrr_set() local
70 mask = ~((uint64_t)size - 1); in do_mtrr_set()
71 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; in do_mtrr_set()
73 mask |= MTRR_PHYS_MASK_VALID; in do_mtrr_set()
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/
H A Dgpio.c11 u32 mask = BIT(gpio); in mscc_gpio_set_alternate() local
18 val0 |= mask; in mscc_gpio_set_alternate()
19 val1 &= ~mask; in mscc_gpio_set_alternate()
21 val0 &= ~mask; in mscc_gpio_set_alternate()
22 val1 |= mask; in mscc_gpio_set_alternate()
24 val0 |= mask; in mscc_gpio_set_alternate()
25 val1 |= mask; in mscc_gpio_set_alternate()
27 val0 &= ~mask; in mscc_gpio_set_alternate()
28 val1 &= ~mask; in mscc_gpio_set_alternate()
/openbmc/u-boot/arch/arm/mach-zynqmp/
H A Dpsu_spl_init.c13 int __maybe_unused mask_pollonvalue(unsigned long add, u32 mask, u32 value) in mask_pollonvalue() argument
17 while ((__raw_readl(add) & mask) != value) { in mask_pollonvalue()
25 __weak int mask_poll(u32 add, u32 mask) in mask_poll() argument
30 while (!(__raw_readl(addr) & mask)) { in mask_poll()
38 __weak u32 mask_read(u32 add, u32 mask) in mask_read() argument
42 return __raw_readl(addr) & mask; in mask_read()
50 __weak void psu_mask_write(unsigned long offset, unsigned long mask, in psu_mask_write() argument
56 regval &= ~(mask); in psu_mask_write()
57 regval |= (val & mask); in psu_mask_write()
61 __weak void prog_reg(unsigned long addr, unsigned long mask, in prog_reg() argument
[all …]
/openbmc/u-boot/drivers/power/regulator/
H A Drk8xx.c104 int mask = info->vsel_mask; in _buck_set_value() local
110 debug("%s: reg=%x, mask=%x, val=%x\n", __func__, info->vsel_reg, mask, in _buck_set_value()
113 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); in _buck_set_value()
118 uint mask; in _buck_set_enable() local
122 mask = 1 << buck; in _buck_set_enable()
132 return pmic_clrsetbits(pmic, REG_DCDC_EN, mask, enable ? mask : 0); in _buck_set_enable()
152 int mask = info->vsel_mask; in buck_get_value() local
160 val = ret & mask; in buck_get_value()
183 uint mask; in buck_get_enable() local
185 mask = 1 << buck; in buck_get_enable()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.core_prefetch7 Here 0x02 can be replaced with any valid value except Mask[0] bit. It
8 represents 64 bit mask. The 64-bit Mask has one bit for each core.
9 Mask[0] = core0
10 Mask[1] = core1
11 Mask[2] = core2
13 If the bit is set ('b1) in the mask, then prefetch is disabled for
16 core0 prefetch should not be disabled i.e. Mask[0] should never be set.
17 Setting Mask[0] may lead to undefined behavior.
/openbmc/u-boot/board/ti/beagle/
H A Dled.c29 static int get_led_gpio(led_id_t mask) in get_led_gpio() argument
32 if (CONFIG_LED_STATUS_BIT & mask) in get_led_gpio()
36 if (CONFIG_LED_STATUS_BIT1 & mask) in get_led_gpio()
43 void __led_init (led_id_t mask, int state) in __led_init() argument
47 toggle_gpio = get_led_gpio(mask); in __led_init()
50 __led_set(mask, state); in __led_init()
53 void __led_toggle (led_id_t mask) in __led_toggle() argument
57 toggle_gpio = get_led_gpio(mask); in __led_toggle()
64 void __led_set (led_id_t mask, int state) in __led_set() argument
68 toggle_gpio = get_led_gpio(mask); in __led_set()
/openbmc/u-boot/arch/nds32/include/asm/
H A Dbitops.h40 int mask; in __set_bit() local
43 mask = 1 << (nr & 0x1f); in __set_bit()
44 *a |= mask; in __set_bit()
54 int mask; in __clear_bit() local
58 mask = 1 << (nr & 0x1f); in __clear_bit()
60 *a &= ~mask; in __clear_bit()
70 int mask; in __change_bit() local
74 mask = 1 << (nr & 31); in __change_bit()
75 *ADDR ^= mask; in __change_bit()
82 int mask, retval; in __test_and_set_bit() local
[all …]
/openbmc/u-boot/arch/nios2/include/asm/bitops/
H A Dnon-atomic.h17 unsigned long mask = BIT_MASK(nr); in __set_bit() local
20 *p |= mask; in __set_bit()
27 unsigned long mask = BIT_MASK(nr); in __clear_bit() local
30 *p &= ~mask; in __clear_bit()
46 unsigned long mask = BIT_MASK(nr); in __change_bit() local
49 *p ^= mask; in __change_bit()
63 unsigned long mask = BIT_MASK(nr); in __test_and_set_bit() local
67 *p = old | mask; in __test_and_set_bit()
68 return (old & mask) != 0; in __test_and_set_bit()
82 unsigned long mask = BIT_MASK(nr); in __test_and_clear_bit() local
[all …]

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