| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr3.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
21 - const: jedec,lpddr3
23 - pattern: "^lpddr3-[0-9a-f]{2},[0-9a-f]{4}$"
24 - const: jedec,lpddr3
177 $ref: jedec,lpddr3-timings.yaml
179 The lpddr3 node may have one or more child nodes with timings.
193 lpddr3 {
194 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
221 compatible = "jedec,lpddr3-timings";
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| H A D | jedec,lpddr-channel.yaml | 22 - jedec,lpddr3-channel
76 const: jedec,lpddr3-channel
80 $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
113 compatible = "jedec,lpddr3-channel";
117 compatible = "lpddr3-ff,0100", "jedec,lpddr3";
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| H A D | jedec,lpddr3-timings.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
14 const: jedec,lpddr3-timings
133 lpddr3 {
135 compatible = "jedec,lpddr3-timings";
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 178 When the DRAM type is LPDDR3, this parameter defines then ODT disable
186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
202 When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
210 When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
218 When dram type is LPDDR3, this parameter define the phy side odt
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| H A D | nvidia,tegra124-mc.yaml | 18 for DDR3L and LPDDR3 SDRAMs.
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| H A D | samsung,exynos5422-dmc.yaml | 56 refer to jedec,lpddr3.yaml.
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| /openbmc/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk3288.c | 249 case LPDDR3: in pctl_cfg()
318 case LPDDR3: in phy_cfg()
324 /* DDRMODE select LPDDR3 */ in phy_cfg()
486 if (sdram_params->base.dramtype != LPDDR3) in data_training()
526 if (sdram_params->base.dramtype != LPDDR3) in data_training()
657 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
790 (sdram_params->base.dramtype == LPDDR3 && in sdram_init()
832 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
871 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
872 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ in sdram_init()
[all …]
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| H A D | sdram_rk3399.c | 176 } else if (sdram_params->base.dramtype == LPDDR3) { in set_ds_odt()
311 } else if (sdram_params->base.dramtype == LPDDR3) { in phy_io_config()
313 vref_mode_dq = 0x5; /* LPDDR3 ODT */ in phy_io_config()
366 vref_mode_dq = 0x2; /* LPDDR3 */ in phy_io_config()
400 else if (sdram_params->base.dramtype == LPDDR3) in phy_io_config()
869 } else if (sdram_params->base.dramtype == LPDDR3) { in data_training()
879 /* ca training(LPDDR4,LPDDR3 support) */ in data_training()
883 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ in data_training()
887 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ in data_training()
891 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ in data_training()
[all …]
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| H A D | sdram_rk3188.c | 428 if (sdram_params->base.dramtype != LPDDR3) in data_training()
468 if (sdram_params->base.dramtype != LPDDR3) in data_training()
604 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
776 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
784 /* DDR3 and LPDDR3 are always 8 bank, no need detect */ in sdram_init()
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| /openbmc/u-boot/doc/device-tree-bindings/memory-controllers/ |
| H A D | st,stm32mp1-ddr.txt | 1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
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| /openbmc/u-boot/arch/x86/include/asm/arch-broadwell/ |
| H A D | pei_data.h | 134 * LPDDR3 DQ byte map
155 * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | Kconfig | 10 family: support for LPDDR2, LPDDR3 and DDR3
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun50i_h6.c | 447 /* TODO: half DQ, non-LPDDR3 types */ in mctl_com_init()
458 /* TODO: non-LPDDR3 types */ in mctl_com_init()
542 /* TODO: non-LPDDR3 types */ in mctl_channel_init()
573 /* TODO: non-LPDDR3 types */ in mctl_channel_init()
604 /* TODO: non-LPDDR3 types */ in mctl_channel_init()
609 /* TODO: non-LPDDR3 types */ in mctl_channel_init()
680 /* TODO: non-LPDDR3, half DQ */ in mctl_auto_detect_dram_size()
711 /* TODO: non-LPDDR3, half DQ */ in mctl_calc_size()
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| H A D | dram_sun9i.c | 492 * LPDDR2 and/or LPDDR3 require a 200us minimum delay in mctl_channel_init()
523 * rd2wr = RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL (for LPDDR2/LPDDR3) in mctl_channel_init()
544 * this is only relevant for LPDDR2/LPDDR3 in mctl_channel_init()
555 /* These timings are relevant for LPDDR2/LPDDR3 only */ in mctl_channel_init()
628 /* For LPDDR2 or LPDDR3, set DQSGX to 0 before training. */ in mctl_channel_init()
653 /* tDQSCK and tDQSCKmax are used LPDDR2/LPDDR3 */ in mctl_channel_init()
673 /* LPDDR2 or LPDDR3 */ in mctl_channel_init()
768 * LPDDR2 and LPDDR3 * in mctl_channel_init()
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| H A D | Kconfig | 380 bool "LPDDR3 with Allwinner stock configuration"
383 This option is the LPDDR3 timing used by the stock boot0 by
402 Set the dram type, 3: DDR3, 7: LPDDR3
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | rk3399-rock960.dts | 8 #include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
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| H A D | rk3399-gru-bob.dts | 10 #include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
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| /openbmc/linux/drivers/memory/ |
| H A D | of_memory.c | 157 * of_lpddr3_get_min_tck() - extract min timing values for lpddr3
244 * of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of
267 tim_compat = "jedec,lpddr3-timings"; in of_lpddr3_get_ddr_timings()
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| H A D | jedec_ddr.h | 221 * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
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| /openbmc/u-boot/board/google/ |
| H A D | Kconfig | 48 LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram.h | 13 LPDDR3 = 6, enumerator
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| H A D | sdram_rk3399.h | 12 LPDDR3 = 0x6, enumerator
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| H A D | sdram_rk3036.h | 317 * 110: lpddr3
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| /openbmc/u-boot/arch/arm/mach-rockchip/rk3399/ |
| H A D | Kconfig | 45 * 2GiB/4GiB LPDDR3 RAM
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| /openbmc/u-boot/arch/x86/dts/ |
| H A D | chromebook_samus.dts | 288 hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
362 hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
401 hynix-h9ccnnncltmlar-lpddr3 {
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