10b381301SKrzysztof Kozlowski# SPDX-License-Identifier: GPL-2.0 20b381301SKrzysztof Kozlowski%YAML 1.2 30b381301SKrzysztof Kozlowski--- 40b381301SKrzysztof Kozlowski$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml# 50b381301SKrzysztof Kozlowski$schema: http://devicetree.org/meta-schemas/core.yaml# 60b381301SKrzysztof Kozlowski 70b381301SKrzysztof Kozlowskititle: | 80b381301SKrzysztof Kozlowski Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory 90b381301SKrzysztof Kozlowski Controller device 100b381301SKrzysztof Kozlowski 110b381301SKrzysztof Kozlowskimaintainers: 128a1e6bb3SKrzysztof Kozlowski - Krzysztof Kozlowski <krzk@kernel.org> 130b381301SKrzysztof Kozlowski - Lukasz Luba <lukasz.luba@arm.com> 140b381301SKrzysztof Kozlowski 150b381301SKrzysztof Kozlowskidescription: | 160b381301SKrzysztof Kozlowski The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the 170b381301SKrzysztof Kozlowski DRAM memory chips are connected. The driver is to monitor the controller in 180b381301SKrzysztof Kozlowski runtime and switch frequency and voltage. To monitor the usage of the 190b381301SKrzysztof Kozlowski controller in runtime, the driver uses the PPMU (Platform Performance 200b381301SKrzysztof Kozlowski Monitoring Unit), which is able to measure the current load of the memory. 210b381301SKrzysztof Kozlowski When 'userspace' governor is used for the driver, an application is able to 220b381301SKrzysztof Kozlowski switch the DMC and memory frequency. 230b381301SKrzysztof Kozlowski 240b381301SKrzysztof Kozlowskiproperties: 250b381301SKrzysztof Kozlowski compatible: 260b381301SKrzysztof Kozlowski items: 270b381301SKrzysztof Kozlowski - const: samsung,exynos5422-dmc 280b381301SKrzysztof Kozlowski 290b381301SKrzysztof Kozlowski clock-names: 300b381301SKrzysztof Kozlowski items: 310b381301SKrzysztof Kozlowski - const: fout_spll 320b381301SKrzysztof Kozlowski - const: mout_sclk_spll 330b381301SKrzysztof Kozlowski - const: ff_dout_spll2 340b381301SKrzysztof Kozlowski - const: fout_bpll 350b381301SKrzysztof Kozlowski - const: mout_bpll 360b381301SKrzysztof Kozlowski - const: sclk_bpll 370b381301SKrzysztof Kozlowski - const: mout_mx_mspll_ccore 380b381301SKrzysztof Kozlowski - const: mout_mclk_cdrex 390b381301SKrzysztof Kozlowski 400b381301SKrzysztof Kozlowski clocks: 410b381301SKrzysztof Kozlowski minItems: 8 420b381301SKrzysztof Kozlowski maxItems: 8 430b381301SKrzysztof Kozlowski 440b381301SKrzysztof Kozlowski devfreq-events: 45*69d170c4SRob Herring $ref: /schemas/types.yaml#/definitions/phandle-array 460b381301SKrzysztof Kozlowski minItems: 1 470b381301SKrzysztof Kozlowski maxItems: 16 4839bd2b6aSRob Herring items: 4939bd2b6aSRob Herring maxItems: 1 500b381301SKrzysztof Kozlowski description: phandles of the PPMU events used by the controller. 510b381301SKrzysztof Kozlowski 520b381301SKrzysztof Kozlowski device-handle: 53*69d170c4SRob Herring $ref: /schemas/types.yaml#/definitions/phandle 540b381301SKrzysztof Kozlowski description: | 550b381301SKrzysztof Kozlowski phandle of the connected DRAM memory device. For more information please 5628f81858SKrzysztof Kozlowski refer to jedec,lpddr3.yaml. 570b381301SKrzysztof Kozlowski 580b381301SKrzysztof Kozlowski operating-points-v2: true 590b381301SKrzysztof Kozlowski 600b381301SKrzysztof Kozlowski interrupts: 610b381301SKrzysztof Kozlowski items: 620b381301SKrzysztof Kozlowski - description: DMC internal performance event counters in DREX0 630b381301SKrzysztof Kozlowski - description: DMC internal performance event counters in DREX1 640b381301SKrzysztof Kozlowski 650b381301SKrzysztof Kozlowski interrupt-names: 660b381301SKrzysztof Kozlowski items: 670b381301SKrzysztof Kozlowski - const: drex_0 680b381301SKrzysztof Kozlowski - const: drex_1 690b381301SKrzysztof Kozlowski 700b381301SKrzysztof Kozlowski reg: 710b381301SKrzysztof Kozlowski items: 720b381301SKrzysztof Kozlowski - description: registers of DREX0 730b381301SKrzysztof Kozlowski - description: registers of DREX1 740b381301SKrzysztof Kozlowski 750b381301SKrzysztof Kozlowski samsung,syscon-clk: 76*69d170c4SRob Herring $ref: /schemas/types.yaml#/definitions/phandle 770b381301SKrzysztof Kozlowski description: | 780b381301SKrzysztof Kozlowski Phandle of the clock register set used by the controller, these registers 790b381301SKrzysztof Kozlowski are used for enabling a 'pause' feature and are not exposed by clock 800b381301SKrzysztof Kozlowski framework but they must be used in a safe way. The register offsets are 810b381301SKrzysztof Kozlowski in the driver code and specyfic for this SoC type. 820b381301SKrzysztof Kozlowski 830b381301SKrzysztof Kozlowski vdd-supply: true 840b381301SKrzysztof Kozlowski 850b381301SKrzysztof Kozlowskirequired: 860b381301SKrzysztof Kozlowski - compatible 870b381301SKrzysztof Kozlowski - clock-names 880b381301SKrzysztof Kozlowski - clocks 890b381301SKrzysztof Kozlowski - devfreq-events 900b381301SKrzysztof Kozlowski - device-handle 910b381301SKrzysztof Kozlowski - reg 920b381301SKrzysztof Kozlowski - samsung,syscon-clk 930b381301SKrzysztof Kozlowski 940b381301SKrzysztof KozlowskiadditionalProperties: false 950b381301SKrzysztof Kozlowski 960b381301SKrzysztof Kozlowskiexamples: 970b381301SKrzysztof Kozlowski - | 980b381301SKrzysztof Kozlowski #include <dt-bindings/clock/exynos5420.h> 990b381301SKrzysztof Kozlowski ppmu_dmc0_0: ppmu@10d00000 { 1000b381301SKrzysztof Kozlowski compatible = "samsung,exynos-ppmu"; 1010b381301SKrzysztof Kozlowski reg = <0x10d00000 0x2000>; 1020b381301SKrzysztof Kozlowski clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; 1030b381301SKrzysztof Kozlowski clock-names = "ppmu"; 1040b381301SKrzysztof Kozlowski events { 1050b381301SKrzysztof Kozlowski ppmu_event_dmc0_0: ppmu-event3-dmc0-0 { 1060b381301SKrzysztof Kozlowski event-name = "ppmu-event3-dmc0_0"; 1070b381301SKrzysztof Kozlowski }; 1080b381301SKrzysztof Kozlowski }; 1090b381301SKrzysztof Kozlowski }; 1100b381301SKrzysztof Kozlowski 1110b381301SKrzysztof Kozlowski memory-controller@10c20000 { 1120b381301SKrzysztof Kozlowski compatible = "samsung,exynos5422-dmc"; 1130b381301SKrzysztof Kozlowski reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; 1140b381301SKrzysztof Kozlowski clocks = <&clock CLK_FOUT_SPLL>, 1150b381301SKrzysztof Kozlowski <&clock CLK_MOUT_SCLK_SPLL>, 1160b381301SKrzysztof Kozlowski <&clock CLK_FF_DOUT_SPLL2>, 1170b381301SKrzysztof Kozlowski <&clock CLK_FOUT_BPLL>, 1180b381301SKrzysztof Kozlowski <&clock CLK_MOUT_BPLL>, 1190b381301SKrzysztof Kozlowski <&clock CLK_SCLK_BPLL>, 1200b381301SKrzysztof Kozlowski <&clock CLK_MOUT_MX_MSPLL_CCORE>, 1210b381301SKrzysztof Kozlowski <&clock CLK_MOUT_MCLK_CDREX>; 1220b381301SKrzysztof Kozlowski clock-names = "fout_spll", 1230b381301SKrzysztof Kozlowski "mout_sclk_spll", 1240b381301SKrzysztof Kozlowski "ff_dout_spll2", 1250b381301SKrzysztof Kozlowski "fout_bpll", 1260b381301SKrzysztof Kozlowski "mout_bpll", 1270b381301SKrzysztof Kozlowski "sclk_bpll", 1280b381301SKrzysztof Kozlowski "mout_mx_mspll_ccore", 1290b381301SKrzysztof Kozlowski "mout_mclk_cdrex"; 1300b381301SKrzysztof Kozlowski operating-points-v2 = <&dmc_opp_table>; 1310b381301SKrzysztof Kozlowski devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, 1320b381301SKrzysztof Kozlowski <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; 1330b381301SKrzysztof Kozlowski device-handle = <&samsung_K3QF2F20DB>; 1340b381301SKrzysztof Kozlowski vdd-supply = <&buck1_reg>; 1350b381301SKrzysztof Kozlowski samsung,syscon-clk = <&clock>; 1360b381301SKrzysztof Kozlowski interrupt-parent = <&combiner>; 1370b381301SKrzysztof Kozlowski interrupts = <16 0>, <16 1>; 1380b381301SKrzysztof Kozlowski interrupt-names = "drex_0", "drex_1"; 1390b381301SKrzysztof Kozlowski }; 140