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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-channel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR channel with chip/rank topology description
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
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/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3288.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
12 #include <dt-structs.h>
102 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_reset()
115 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_phy_ctl_reset()
121 int channel) in phy_pctrl_reset() argument
125 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
127 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
129 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
132 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
134 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
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H A Dsdram_rk3399.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * (C) Copyright 2016-2017 Rockchip Inc.
11 #include <dt-structs.h>
83 u32 *denali_phy = ddr_publ_regs->denali_phy; in phy_dll_bypass_set()
111 static void set_memory_map(const struct chan_info *chan, u32 channel, in set_memory_map() argument
115 &sdram_params->ch[channel]; in set_memory_map()
116 u32 *denali_ctl = chan->pctl->denali_ctl; in set_memory_map()
117 u32 *denali_pi = chan->pi->denali_pi; in set_memory_map()
123 if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4) in set_memory_map()
125 else if (sdram_ch->ddrconfig == 3) in set_memory_map()
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H A Dsdram_rk3188.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
12 #include <dt-structs.h>
103 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_reset()
116 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_phy_ctl_reset()
122 int channel) in phy_pctrl_reset() argument
126 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
128 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
130 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
133 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
135 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
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/openbmc/u-boot/arch/x86/include/asm/arch-broadwell/
H A Dpei_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
87 * 0 = leave channel enabled
88 * 1 = disable dimm 0 on channel
89 * 2 = disable dimm 1 on channel
90 * 3 = disable dimm 0+1 on channel
115 /* Valid range: 0x69 - 0x80 */
117 /* Valid range: 0x80 - 0x9c */
119 /* Valid range: 0x39 - 0x80 */
121 /* Valid range: 0x3d - 0x4a */
129 * [CHANNEL][SLOT][SPD]
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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015
10 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
26 * Allwinner as part of the open-source bootloader release (refer to
27 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
36 * Note that the Zynq-documentation provides a very close match for the DDR
42 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
48 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
50 * 2) Only 2T-mode has been implemented and tested.
62 * The driver should be driven from a device-tree based configuration that
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/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3399.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
12 LPDDR3 = 0x6, enumerator
38 u32 reserved0[(0x110 - 0x20) / 4];
40 u32 reserved1[(0x1000 - 0x114) / 4];
76 /* dram column number, 0 means this channel is invalid */
80 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10 - clock: must include clock specifiers corresponding to entries in the clock-names property.
11 - clock-output-names: from common clock binding to override the default output clock name
13 pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
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/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_dram.c1 // SPDX-License-Identifier: MIT
34 DRAM_TYPE_STR(LPDDR3), in intel_dram_type_str()
50 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); in pnv_detect_mem_freq()
54 dev_priv->fsb_freq = 533; /* 133*4 */ in pnv_detect_mem_freq()
57 dev_priv->fsb_freq = 800; /* 200*4 */ in pnv_detect_mem_freq()
60 dev_priv->fsb_freq = 667; /* 167*4 */ in pnv_detect_mem_freq()
63 dev_priv->fsb_freq = 400; /* 100*4 */ in pnv_detect_mem_freq()
69 dev_priv->mem_freq = 533; in pnv_detect_mem_freq()
72 dev_priv->mem_freq = 667; in pnv_detect_mem_freq()
75 dev_priv->mem_freq = 800; in pnv_detect_mem_freq()
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/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h1 /* SPDX-License-Identifier: GPL-2.0+ */
68 * As we use channel interleaving, therefore value of the base address
168 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
174 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
408 #define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
409 #define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
889 /* Errors that we can encourter in low-level setup */
892 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
893 SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
905 /* Memory variant specific initialization code for LPDDR3 */
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/openbmc/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__)
53 * PTFV defines - basically just indexes into the per table PTFV array.
78 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \
79 next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] += \
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/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DMemory.v1_20_0.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
64 "description": "The available OEM-specific actions for this resource.",
65 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
105 … "longDescription": "This type shall contain CXL-specific properties for a memory device.",
107 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
130 …"description": "Total device non-volatile memory capacity in MiB staged for next activation. The …
131 …escription": "The value of this property shall indicate the total device non-volatile memory capac…
167 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
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/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/
H A DMemory.v1_20_0.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
64 "description": "The available OEM-specific actions for this resource.",
65 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
105 … "longDescription": "This type shall contain CXL-specific properties for a memory device.",
107 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
130 …"description": "Total device non-volatile memory capacity in MiB staged for next activation. The …
131 …escription": "The value of this property shall indicate the total device non-volatile memory capac…
167 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
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/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datomfirmware.h6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
656 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
657 …eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without A…
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/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DMemory_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: Memory v1.20.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
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/openbmc/bmcweb/redfish-core/schema/dmtf/installed/
H A DMemory_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: Memory v1.20.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
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/openbmc/linux/
H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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