| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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| H A D | jedec,lpddr2-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | elpida_ecb240abacn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 elpida_ECB240ABACN: lpddr2 {
8 compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4";
10 io-width = <32>;
12 tRPab-min-tck = <3>;
13 tRCD-min-tck = <3>;
14 tWR-min-tck = <3>;
15 tRASmin-min-tck = <3>;
16 tRRD-min-tck = <2>;
17 tWTR-min-tck = <2>;
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| /openbmc/linux/drivers/memory/ |
| H A D | of_memory.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * of_get_min_tck() - extract min timing values for ddr
26 * default min timings provided by JEDEC.
38 ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); in of_get_min_tck()
39 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_get_min_tck()
40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
41 ret |= of_property_read_u32(np, "tRASmin-min-tck", &min->tRASmin); in of_get_min_tck()
42 ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); in of_get_min_tck()
43 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_get_min_tck()
44 ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); in of_get_min_tck()
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| H A D | jedec_ddr.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
64 /* Refresh rate in nano-seconds */
96 * LPDDR2 related defines
143 * Structure for timings from the LPDDR2 datasheet
205 * Structure for information about LPDDR2 chip. All parameters are
207 * -ENOENT if info unavailable.
221 * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
97 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
98 This driver takes care of only LPDDR2 memories presently. The
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| H A D | emif.c | 1 // SPDX-License-Identifier: GPL-2.0-only
32 * struct emif_data - Per device static data for driver's use
36 * @temperature_level: Maximum temperature of LPDDR2 devices attached
37 * to this EMIF - read from MR4 register. If there
42 * @base: base address of memory-mapped IO registers.
46 * frequencies, to avoid re-calculating them on
79 u32 type = emif->plat_data->device_info->type; in do_emif_regdump_show()
80 u32 ip_rev = emif->plat_data->ip_rev; in do_emif_regdump_show()
83 regs->freq/1000000); in do_emif_regdump_show()
85 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); in do_emif_regdump_show()
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| /openbmc/linux/include/linux/platform_data/ |
| H A D | emif_plat.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Low power modes - EMIF_PWR_MGMT_CTRL */
23 * EMIF4D - Used in OMAP4
24 * EMIF4D5 - Used in OMAP5
31 * ATTILAPHY - Used in OMAP4
32 * INTELLIPHY - Used in OMAP5
44 * struct ddr_device_info - All information about the DDR device except AC
46 * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc)
50 * chip-select(CS1) of this EMIF instance
52 * chip-select or whether it's a single one for both
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| /openbmc/linux/Documentation/driver-api/memory-devices/ |
| H A D | ti-emif.rst | 1 .. SPDX-License-Identifier: GPL-2.0
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
31 This driver takes care of only LPDDR2 memories presently. The
32 functions of the driver includes re-configuring AC timing
41 - DDR device details: 'struct ddr_device_info'
42 - Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck'
43 - Custom configurations: customizable policy options through
45 - IP revision
46 - PHY type
53 - freq_pre_notify_handling()
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015
10 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
26 * Allwinner as part of the open-source bootloader release (refer to
27 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
36 * Note that the Zynq-documentation provides a very close match for the DDR
38 * rules for various timings), whereas the TI Keystone II document should be
42 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
48 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
50 * 2) Only 2T-mode has been implemented and tested.
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| /openbmc/linux/drivers/memory/tegra/ |
| H A D | tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
206 struct emc_timing *timings; member
221 /* protect shared rate-change code path */
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
262 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
263 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
264 timing = &emc->timings[i]; in tegra_emc_find_timing()
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| H A D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
366 struct emc_timing *timings; member
392 /* protect shared rate-change code path */
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
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| /openbmc/u-boot/arch/arm/mach-imx/ |
| H A D | ddrmc-vf610.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux-vf610.h>
12 #include <asm/arch/ddrmc-vf610.h>
13 #include "ddrmc-vf610-calibration.h"
98 /* LPDDR2 only parameter */
107 { 0, -1 }
110 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, in ddrmc_ctrl_init_ddr3() argument
119 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); in ddrmc_ctrl_init_ddr3()
120 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); in ddrmc_ctrl_init_ddr3()
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| /openbmc/linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra30-asus-tf201.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
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| H A D | tegra20-asus-tf101.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
33 * pre-existing /chosen node to be available to insert the
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra30-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
39 const: nvidia,tegra30-mc
47 clock-names:
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| H A D | nvidia,tegra30-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
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| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | emif-common.c | 1 // SPDX-License-Identifier: GPL-2.0+
19 #include <asm/ti-common/ti-edma3.h>
21 static int emif1_enabled = -1, emif2_enabled = -1;
28 reg = readl(&emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()
32 writel(reg, &emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()
35 readl(&emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()
61 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); in get_mr()
63 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); in get_mr()
65 mr = readl(&emif->emif_lpddr2_mode_reg_data); in get_mr()
81 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); in set_mr()
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | emif.h | 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
808 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
815 * calculations. So, as a trade-off keep denominator(and consequently
816 * numerator) within a limit sacrificing some accuracy - but not much
885 /* Interleaving policies at EMIF level- between banks and Chip Selects */
897 * ZQ calibration timings. Timings are much stricter when voltage ramp
909 /* To be used when voltage is changed for DPS/DVFS - 1us */
913 * 50us - or maximum value will do
921 * due to smart-reflex.
934 /* Enable ZQ Calibration on exiting Self-refresh */
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
168 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
174 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
889 /* Errors that we can encourter in low-level setup */
892 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
893 SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
899 * @param mem Memory timings for this memory type.
911 * @param mem Memory timings for this memory type.
912 * @param phy0_con16 Register address for dmc_phy0->phy_con16
913 * @param phy1_con16 Register address for dmc_phy1->phy_con16
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| /openbmc/linux/ |
| H A D | opengrok1.0.log | 1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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| H A D | opengrok2.0.log | 1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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