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/openbmc/linux/Documentation/devicetree/bindings/ipmi/
H A Daspeed,ast2400-kcs-bmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
13 The Aspeed BMC SoCs typically use the Keyboard-Controller-Style (KCS)
14 interfaces on the LPC bus for in-band IPMI communication with their host.
19 - description: Channel ID derived from reg
22 - aspeed,ast2400-kcs-bmc-v2
23 - aspeed,ast2500-kcs-bmc-v2
[all …]
H A Dnpcm7xx-kcs-bmc.txt5 used to perform in-band IPMI communication with their host.
8 - compatible : should be one of
9 "nuvoton,npcm750-kcs-bmc"
10 "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc"
11 - interrupts : interrupt generated by the controller
12 - kcs_chan : The KCS channel number in the controller
17 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
19 reg-io-width = <1>;
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed-lpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Aspeed Low Pin Count (LPC) Bus Controller
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
[all …]
/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Drtc-st-lpc.txt1 STMicroelectronics Low Power Controller (LPC) - RTC
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dst,stih407-lpc1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../rtc/rtc-st-lpc.txt for RTC options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dst_lpc_wdt.txt1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
7 [See: ../rtc/rtc-st-lpc.txt for RTC options]
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Should be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
24 - st,syscfg : Phandle to syscfg node used to enable watchdog and configure
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dast2400.dtsi3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g4.dtsi
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&vic>;
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm926ej-s";
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
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H A Dast2500.dtsi3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&vic>;
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1176jzf-s";
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
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H A Dast2600.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include <dt-bindings/gpio/aspeed-gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
46 #address-cells = <1>;
47 #size-cells = <0>;
48 enable-method = "aspeed,ast2600-smp";
51 compatible = "arm,cortex-a7";
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H A Dstih407-family.dtsi9 #include "stih407-pinctrl.dtsi"
10 #include <dt-bindings/mfd/st-lpc.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/stih407-resets.h>
13 #include <dt-bindings/interrupt-controller/irq-st.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dlpc-eth.txt4 - compatible: Should be "nxp,lpc-eth"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain ethernet controller interrupt
9 - phy-mode: See ethernet.txt file in the same directory. If the property is
11 - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
14 - mdio : specifies the mdio bus, used as a container for phy nodes according to
21 compatible = "nxp,lpc-eth";
23 interrupt-parent = <&mic>;
24 interrupts = <29 0>;
26 phy-mode = "rmii";
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/openbmc/qemu/include/hw/ppc/
H A Dpnv_lpc.h2 * QEMU PowerPC PowerNV LPC controller
4 * Copyright (c) 2016-2022, IBM Corporation.
25 #include "hw/qdev-core.h"
28 #define TYPE_PNV_LPC "pnv-lpc"
33 #define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8"
37 #define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
41 #define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10"
77 /* LPC device IRQ state */
80 /* LPC HC registers */
98 /* PSI to generate interrupts */
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g4.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
35 #address-cells = <1>;
36 #size-cells = <0>;
39 compatible = "arm,arm926ej-s";
51 compatible = "simple-bus";
52 #address-cells = <1>;
[all …]
H A Daspeed-g6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "aspeed,ast2600-smp";
[all …]
H A Daspeed-g5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "arm,arm1176jzf-s";
52 compatible = "simple-bus";
[all …]
H A Daspeed-bmc-amd-ethanolx.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include "aspeed-g5.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
26 compatible = "shared-dma-pool";
[all …]
/openbmc/phosphor-mboxd/Documentation/
H A Dmbox_protocol.md7 http://www.apache.org/licenses/LICENSE-2.0
38 (the iLPC-to-AHB bridge) to directly manipulate the BMCs own flash controller.
71 "window" (which is the LPC -> AHB FW space mapping) that is either a read
78 The idea is to have the LPC FW space be routed to an active "window". That
95 LPC mapping to point to that buffer.
118 The Autotools of this requires the autoconf-archive package for your
126 Interrupts can also be raised per write to each data register, for BMC and
127 host. Write triggered interrupts are configured using two 8 bit registers where
130 interrupts.
137 Byte 2-12: Arguments
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
[all …]
/openbmc/qemu/hw/ppc/
H A Dpnv_lpc.c2 * QEMU PowerPC PowerNV LPC controller
27 #include "hw/qdev-properties.h"
52 /* LPC HC registers */
105 const char compat[] = "ibm,power8-lpc\0ibm,lpc"; in pnv_lpc_dt_xscom()
120 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); in pnv_lpc_dt_xscom()
121 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); in pnv_lpc_dt_xscom()
130 const char compat[] = "ibm,power9-lpcm-opb\0simple-bus"; in pnv_dt_lpc()
131 const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc"; in pnv_dt_lpc()
163 name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr); in pnv_dt_lpc()
169 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1))); in pnv_dt_lpc()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/security/tpm/
H A Dtpm_tis_mmio.txt5 this interface will be implemented over Intel's LPC bus.
12 - compatible: should contain a string below for the chip, followed by
13 "tcg,tpm-tis-mmio". Valid chip strings are:
15 - reg: The location of the MMIO registers, should be at least 0x5000 bytes
16 - interrupts: An optional interrupt indicating command completion.
21 compatible = "atmel,at97sc3204", "tcg,tpm-tis-mmio";
23 interrupt-parent = <&EIC0>;
24 interrupts = <1 2>;
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_aspeed_vuart.c1 // SPDX-License-Identifier: GPL-2.0+
62 * to the host on the Host <-> BMC LPC bus. It could be different on a
68 return readb(vuart->port->port.membase + reg); in aspeed_vuart_readb()
73 writeb(val, vuart->port->port.membase + reg); in aspeed_vuart_writeb()
91 return -EINVAL; in aspeed_vuart_set_lpc_address()
135 return -EINVAL; in aspeed_vuart_set_sirq()
251 struct aspeed_vuart *vuart = uart_8250_port->port.private_data; in aspeed_vuart_startup()
266 struct aspeed_vuart *vuart = uart_8250_port->port.private_data; in aspeed_vuart_shutdown()
279 lockdep_assert_held_once(&up->port.lock); in __aspeed_vuart_set_throttle()
281 up->ier &= ~irqs; in __aspeed_vuart_set_throttle()
[all …]
/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md1 # Management Component Transport Protocol (MCTP) LPC Transport Binding Specification for ASPEED BMC…
6 host and BMC over the LPC bus on ASPEED BMC platforms.
17 2. Intel (R) Low Pin Count (LPC) Interface Specification 1.1,
18 …<https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-spec…
29 MCTP-compliant endpoints must accept.
33 A hardware-defined flag bit in a KCS device's Status Register (STR). The IBF
42 ### KCS: Keyboard-Controller-Style
48 systems. This interface is available built-in to several commercially available
49 microcontrollers. Data is transferred across the KCS interface using a per-byte
52 ### LPC Bus: Low Pin Count Bus
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/openbmc/linux/drivers/char/
H A Ddtlk.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* -*- linux-c -*-
3 * dtlk.c - DoubleTalk PC driver for Linux
8 * 2000-03-18 Jim Van Zandt: Fix polling.
20 The DoubleTalk PC contains four voice synthesizers: text-to-speech
21 (TTS), linear predictive coding (LPC), PCM/ADPCM, and CVSD. It
22 also has a tone generator. Output data for LPC are written to the
23 LPC port, and output data for the other modes are written to the
29 of the speech) are read from the LPC port. Not all models of the
30 DoubleTalk PC implement index markers. Both the TTS and LPC ports
[all …]

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