| /openbmc/qemu/util/ |
| H A D | hbitmap.c | 9 * later. See the COPYING file in the top-level directory.
14 #include "qemu/host-utils.h"
25 * granularity; in all levels except the last, bit N is set iff the N-th
26 * unsigned long is nonzero in the immediately next level. When iteration
27 * completes on the last level it can examine the 2nd-last level to quickly
29 * powers thereof (32 on 32-bit machines).
32 * this (for the 64-bit case):
34 * bits 0-57 => word in the last bitmap | bits 58-63 => bit in the word
35 * bits 0-51 => word in the 2nd-last bitmap | bits 52-57 => bit in the word
36 * bits 0-45 => word in the 3rd-last bitmap | bits 46-51 => bit in the word
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | cache.json | 105 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
120 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | metrics.json | 89 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
96 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
103 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
117 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
124 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
131 …level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
138 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
145 …ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives a…
152 …"BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per …
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | metrics.json | 4 …"MetricExpr": "(100 * ((STALL_SLOT_BACKEND / (CPU_CYCLES * #slots)) - ((BR_MIS_PRED * 3) / CPU_CYC…
15 …0 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (((STALL_SLOT) if (strcmp_cpuid_str(0x410fd493) | strcmp…
61 …mp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT_FRONTEND - CPU_CYCLES)) / (CPU_CYCLES * #slots)) - …
101 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
108 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
115 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
122 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
129 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
136 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
143 …level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | cache.json | 111 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
114 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
117 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t…
150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th…
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| /openbmc/linux/arch/x86/kvm/mmu/ |
| H A D | tdp_iter.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Recalculates the pointer to the SPTE for the current GFN and level and
14 iter->sptep = iter->pt_path[iter->level - 1] + in tdp_iter_refresh_sptep()
15 SPTE_INDEX(iter->gfn << PAGE_SHIFT, iter->level); in tdp_iter_refresh_sptep()
16 iter->old_spte = kvm_tdp_mmu_read_spte(iter->sptep); in tdp_iter_refresh_sptep()
25 iter->yielded = false; in tdp_iter_restart()
26 iter->yielded_gfn = iter->next_last_level_gfn; in tdp_iter_restart()
27 iter->level = iter->root_level; in tdp_iter_restart()
29 iter->gfn = gfn_round_for_level(iter->next_last_level_gfn, iter->level); in tdp_iter_restart()
32 iter->valid = true; in tdp_iter_restart()
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| /openbmc/linux/kernel/rcu/ |
| H A D | tree.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion (tree-based version)
4 * Internal non-public definitions.
43 * Definition for node within the RCU grace-period-detection hierarchy.
49 unsigned long gp_seq; /* Track rsp->gp_seq. */
60 /* Per-GP initial value for qsmask. */
61 /* Initialized from ->qsmaskinitnext at the */
68 /* Per-GP initial values for expmask. */
69 /* Initialized from ->expmaskinitnext at the */
80 int grplo; /* lowest-numbered CPU here. */
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| /openbmc/linux/Documentation/admin-guide/mm/ |
| H A D | numaperf.rst | 21 +------------------+ +------------------+
22 | Compute Node 0 +-----+ Compute Node 1 |
24 +--------+---------+ +--------+---------+
26 +--------+---------+ +--------+---------+
28 +------------------+ +--------+---------+
36 performance when accessing a given memory target. Each initiator-target
48 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
49 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
51 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
52 relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
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| /openbmc/linux/drivers/net/wireless/ath/ath5k/ |
| H A D | ani.c | 33 * - "noise immunity"
35 * - "spur immunity"
37 * - "firstep level"
39 * - "OFDM weak signal detection"
41 * - "CCK weak signal detection"
61 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
63 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL
66 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_noise_immunity_level() argument
70 * and ath9k use only the last two levels, making this in ath5k_ani_set_noise_immunity_level()
75 static const s8 lo[] = { -52, -56, -60, -64, -70 }; in ath5k_ani_set_noise_immunity_level()
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| /openbmc/qemu/target/riscv/ |
| H A D | monitor.c | 2 * QEMU monitor for RISC-V
6 * RISC-V specific monitor commands implementation
25 #include "monitor/hmp-target.h"
30 #define PTE_HEADER_DELIMITER "---------------- ---------------- "\
31 "---------------- -------\n"
34 #define PTE_HEADER_DELIMITER "-------- ---------------- -------- -------\n"
41 if (addr & (1UL << (va_bits - 1))) { in addr_canonical()
42 addr |= (hwaddr)-(1L << va_bits); in addr_canonical()
71 attr & PTE_R ? 'r' : '-', in print_pte()
72 attr & PTE_W ? 'w' : '-', in print_pte()
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| /openbmc/linux/Documentation/arch/arm/ |
| H A D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
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| /openbmc/linux/tools/perf/Documentation/ |
| H A D | itrace.txt | 10 of aux-output (refer to perf record)
15 f synthesize first level cache events
16 m synthesize last level cache events
22 l synthesize last branch entries (use with i or x)
23 L synthesize last branch entries on existing event records
27 Z prefer to ignore timestamps (so-called "timeless" decoding)
29 The default is all events i.e. the same as --itrace=iybxwpe,
30 except for perf script where it is --itrace=ce
44 Also the number of last branch entries (default 64, max. 1024) for
49 large PEBS. Refer linkperf:perf-intel-pt[1] man page for details.
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| /openbmc/linux/fs/xfs/scrub/ |
| H A D | bitmap.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2018-2023 Oracle. All Rights Reserved.
25 /* Last set bit of this interval. */
28 /* Last set bit of this subtree. Do not touch this. */
34 #define START(node) ((node)->bn_start)
35 #define LAST(node) ((node)->bn_last) macro
39 * forward-declare them anyway for clarity.
49 uint64_t last);
53 uint64_t last);
56 __bn_subtree_last, START, LAST, static inline, xbitmap_tree) in INTERVAL_TREE_DEFINE() argument
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| /openbmc/linux/include/linux/ |
| H A D | amd-pstate.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/amd-pstate.h
21 * AMD P-state INTERFACE *
36 * struct amd_cpudata - private CPU data for AMD P-State
42 * @nominal_perf: the maximum sustained performance level of the processor,
44 * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power
46 * @lowest_perf: the absolute lowest performance level of the processor
51 * @cur: Difference of Aperf/Mperf/tsc count between last and current sample
52 * @prev: Last Aperf/Mperf/tsc count value read from register
57 * AMD P-State driver supports preferred core featue.
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/ |
| H A D | common-and-microarch.json | 9 "PublicDescription": "Level 1 instruction cache refill",
12 "BriefDescription": "Level 1 instruction cache refill"
15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
21 "PublicDescription": "Level 1 data cache refill",
24 "BriefDescription": "Level 1 data cache refill"
27 "PublicDescription": "Level 1 data cache access",
30 "BriefDescription": "Level 1 data cache access"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
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| /openbmc/linux/drivers/md/bcache/ |
| H A D | btree.c | 1 // SPDX-License-Identifier: GPL-2.0
21 * All configuration is done via sysfs; see Documentation/admin-guide/bcache.rst.
100 (((k)->ptr[0] >> c->bucket_bits) | PTR_GEN(k, 0))
104 #define insert_lock(s, b) ((b)->level <= (s)->lock)
109 return ((void *) btree_bset_first(b)) + b->written * block_bytes(b->c->cache); in write_block()
115 if (b->level && b->keys.nsets) in bch_btree_init_next()
116 bch_btree_sort(&b->keys, &b->c->sort); in bch_btree_init_next()
118 bch_btree_sort_lazy(&b->keys, &b->c->sort); in bch_btree_init_next()
120 if (b->written < btree_blocks(b)) in bch_btree_init_next()
121 bch_bset_init_next(&b->keys, write_block(b), in bch_btree_init_next()
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| /openbmc/linux/Documentation/devicetree/bindings/cache/ |
| H A D | qcom,llcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Bjorn Andersson <andersson@kernel.org>
13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
23 - qcom,sc7180-llcc
24 - qcom,sc7280-llcc
25 - qcom,sc8180x-llcc
26 - qcom,sc8280xp-llcc
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| /openbmc/linux/drivers/staging/vc04_services/bcm2835-camera/ |
| H A D | bcm2835-camera.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
81 /* H264 level */
83 /* JPEG Q-factor */
92 /* Sequence number of last buffer */
102 /* last frame completion */
120 #define v4l2_dump_pix_format(level, debug, dev, pix_fmt, desc) \ argument
122 v4l2_dbg(level, debug, dev, \
125 (pix_fmt)->width, (pix_fmt)->height, (pix_fmt)->field, \
126 (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \
127 (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \
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| /openbmc/ipmi-fru-parser/ |
| H A D | writefrudata.cpp | 10 #include <phosphor-logging/log.hpp>
39 * Must always be called as last reference to fruFilePointer.
41 * @param[in] fruFilePointer - FRU file pointer to close
42 * @param[in] fruAreaVec - vector of FRU areas
43 * @return -1
57 return -1; in cleanupError()
64 * @param[in] section - FRU section name
65 * @param[in] key - key for section
66 * @param[in] delimiter - delimiter for parsing custom fields
67 * @param[in] fruData - the FRU data to search for the section
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| /openbmc/linux/fs/xfs/libxfs/ |
| H A D | xfs_btree.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2002,2005 Silicon Graphics, Inc.
49 /* Ensure we asked for crc for crc-only magics. */ in xfs_btree_magic()
61 * on x86-64. Yes, gcc-11 fails to inline them, and explicit inlining of these
69 int level, in xfs_btree_check_lblock_siblings() argument
81 if (level >= 0) { in xfs_btree_check_lblock_siblings()
82 if (!xfs_btree_check_lptr(cur, sibling, level + 1)) in xfs_btree_check_lblock_siblings()
96 int level, in xfs_btree_check_sblock_siblings() argument
108 if (level >= 0) { in xfs_btree_check_sblock_siblings()
109 if (!xfs_btree_check_sptr(cur, sibling, level + 1)) in xfs_btree_check_sblock_siblings()
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| H A D | xfs_btree.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2000-2001,2005 Silicon Graphics, Inc.
28 * The in-core btree key. Overlapping btrees actually store two keys
52 * This nonsense is to make -wlint happy.
81 #define XFS_BB_ALL_BITS ((1u << XFS_BB_NUM_BITS) - 1)
83 #define XFS_BB_ALL_BITS_CRC ((1u << XFS_BB_NUM_BITS_CRC) - 1)
89 XFS_STATS_INC_OFF((cur)->bc_mp, (cur)->bc_statoff + __XBTS_ ## stat)
91 XFS_STATS_ADD_OFF((cur)->bc_mp, (cur)->bc_statoff + __XBTS_ ## stat, val)
135 /* update last record information */
141 /* records in block/level */
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| /openbmc/linux/arch/arm64/kernel/ |
| H A D | head.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level CPU initialisation
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
21 #include <asm/asm-offsets.h>
27 #include <asm/kernel-pgtable.h>
30 #include <asm/pgtable-hwdef.h>
38 #include "efi-header.S"
46 * ---------------------------
49 * MMU = off, D-cache = off, I-cache = on or off,
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| /openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z14/ |
| H A D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
21 …e data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on thi…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Las…
31 "Unit": "CPU-M-CF",
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-led | 9 just be turned on for non-zero brightness settings.
23 Documentation/leds/leds-class-multicolor.rst.
30 Writing non-zero to this file while trigger is active changes the
40 Maximum brightness level for this LED, default is 255 (LED_FULL).
49 Last hardware set brightness level for this LED. Some LEDs
57 Reading this file will return the last brightness level set
73 their documentation see `sysfs-class-led-trigger-*`.
|
| /openbmc/linux/drivers/usb/serial/ |
| H A D | io_16654.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
72 #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level
73 #define FCR_TX_LEVEL_8 0x00 // Tx FIFO Level = 8 bytes
74 #define FCR_TX_LEVEL_16 0x10 // Tx FIFO Level = 16 bytes
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