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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dti,j721e-system-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@ti.com>
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
15 for achieving various system level goals.
17 These processor sub-systems usually contain additional sub-modules like
18 L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
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H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
18 on the SoC to achieve various system level goals.
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
27 Each Dual-Core R5F sub-system is represented as a single DTS node
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
22 Complex (UDMA-P) controller.
43 device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
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H A Dti,k3-am654-cpts.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E CPTS module is used to facilitate host control of time
17 - selection of multiple external clock sources
18 - Software control of time sync events via interrupt or polling
[all …]
/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Dti,j721e-esm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neha Malcom Francis <n-francis@ti.com>
16 controller would do. The safety signals have their separate paths within
18 destination, which can be system reset, interrupt controller, etc. In the
23 const: ti,j721e-esm
28 ti,esm-pins:
29 $ref: /schemas/types.yaml#/definitions/uint32-array
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,pruss-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
22 The property "ti,irqs-reserved" is used for denoting the connection
26 controller.
30 through 19) are connected to new sub-modules within the ICSSG instances.
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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 bootph-all;
11 compatible = "ti,k2g-sci";
12 ti,host-id = <12>;
14 mbox-names = "rx", "tx";
19 reg-names = "debug_messages";
22 k3_pds: power-controller {
23 bootph-all;
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H A Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
[all …]
H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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H A Dk3-j7200-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
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H A Dk3-j721s2-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
H A Dk3-am62a-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 compatible = "ti,am654-chipid";
23 compatible = "ti,am64-uart", "ti,am654-uart";
26 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
28 clock-names = "fclk";
33 compatible = "ti,am64-i2c", "ti,omap4-i2c";
[all …]
H A Dk3-j721e-common-proc-board.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e-som-p0.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
14 #include <dt-bindings/phy/phy-cadence.h>
17 compatible = "ti,j721e-evm", "ti,j721e";
18 model = "Texas Instruments J721e EVM";
[all …]
H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
25 #address-cells = <2>;
26 #size-cells = <2>;
28 #interrupt-cells = <3>;
[all …]
H A Dk3-j7200-common-proc-board.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy.h>
13 #include "k3-serdes.h"
16 compatible = "ti,j7200-evm", "ti,j7200";
30 stdout-path = "serial2:115200n8";
[all …]
H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
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/openbmc/linux/drivers/usb/cdns3/
H A DKconfig7 Say Y here if your system has a Cadence USBSS or USBSSP
8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
30 bool "Cadence USB3 device controller"
33 Say Y here to enable device controller functionality of the
34 Cadence USBSS-DEV driver.
36 This controller supports FF, HS and SS mode. It doesn't support
[all …]
/openbmc/linux/drivers/dma/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 Enable support for the TI EDMA (Enhanced DMA) controller. This DMA
27 tristate "Texas Instruments sDMA (omap-dma) support"
34 Enable support for the TI sDMA (System DMA or DMA4) controller. This
47 Enable support for the TI UDMA (Unified DMA) controller. This
48 DMA engine is used in AM65x and j721e.
/openbmc/linux/drivers/remoteproc/
H A Dpru_rproc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PRU-ICSS remoteproc driver for various TI SoCs
5 * Copyright (C) 2014-2022 Texas Instruments Incorporated - https://www.ti.com/
8 * Suman Anna <s-anna@ti.com>
11 * Puranjay Mohan <p-mohan@ti.com>
41 /* CTRL register bit-fields */
71 * enum pru_iomem - PRU core memory/register range identifiers
86 * struct pru_private_data - device data for a PRU core
96 * struct pru_rproc - PRU remoteproc structure
99 * @pruss: back-reference to parent PRUSS structure
[all …]
/openbmc/linux/drivers/mmc/host/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # MMC/SD host controller drivers
6 comment "MMC/SD/SDIO Host Controller Drivers"
18 tristate "Sunplus SP7021 MMC Controller"
37 bool "Qualcomm Data Mover for SD Card Controller"
41 This selects the Qualcomm Data Mover lite/local on SD Card controller.
48 bool "STMicroelectronics STM32 SDMMC Controller"
52 This selects the STMicroelectronics STM32 SDMMC host controller.
68 tristate "Secure Digital Host Controller Interface support"
71 This selects the generic Secure Digital Host Controller Interface.
[all …]
/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
19 it has been replaced by a better system and you
21 W: *Web-page* with status/info
22 Q: *Patchwork* web based patch tracking system site
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
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