Home
last modified time | relevance | path

Searched +full:irq +full:- +full:syscfg (Results 1 – 25 of 55) sorted by relevance

123

/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
19 const: st,stih407-irq-syscfg
21 st,syscfg:
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
27 $ref: /schemas/types.yaml#/definitions/uint32-array
[all …]
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_syscfg-test.c4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * See the COPYING file in the top-level directory.
12 #include "libqtest-single.h"
29 /* SoC forwards GPIOs to SysCfg */
31 #define SYSCFG "/machine/soc/syscfg" macro
32 #define SYSCFG_CLK "/machine/soc/syscfg/clk"
203 * Test that GPIO rising lines result in an irq in test_interrupt()
228 /* irq 15 is high at reset because GPIOA15 is high at reset */ in test_interrupt()
236 * Test that syscfg irq sets the right exti irq in test_irq_pin_multiplexer()
[all …]
H A Dstm32l4x5_gpio-test.c4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * See the COPYING file in the top-level directory.
12 #include "libqtest-single.h"
47 /* SoC forwards GPIOs to SysCfg */
48 #define SYSCFG "/machine/soc" macro
84 #define GPIO_ADDR_MASK (~(GPIO_SIZE - 1))
121 return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE; in get_gpio_id()
137 r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': " in disconnect_all_pins()
138 "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }", in disconnect_all_pins()
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-st.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * This is a re-write of Christophe Kerello's PMU driver.
10 #include <dt-bindings/interrupt-controller/irq-st.h>
38 unsigned int syscfg; member
45 .compatible = "st,stih407-irq-syscfg",
52 int device, int channel, bool irq) in st_irq_xlate() argument
54 struct st_irq_syscfg *ddata = dev_get_drvdata(&pdev->dev); in st_irq_xlate()
59 ddata->config |= ST_A9_IRQ_EN_EXT_0; in st_irq_xlate()
62 ddata->config |= ST_A9_IRQ_EN_EXT_1; in st_irq_xlate()
65 ddata->config |= ST_A9_IRQ_EN_EXT_2; in st_irq_xlate()
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dstm32-adc-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
8 * Inspired from: fsl-imx25-tsadc
29 #include "stm32-adc-core.h"
33 /* SYSCFG registers */
37 /* SYSCFG bit fields */
40 /* SYSCFG capability flags */
45 * struct stm32_adc_common_regs - stm32 common registers
65 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
70 * @has_syscfg: SYSCFG capability flags
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstih407-family.dtsi9 #include "stih407-pinctrl.dtsi"
10 #include <dt-bindings/mfd/st-lpc.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/stih407-resets.h>
13 #include <dt-bindings/interrupt-controller/irq-st.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
[all …]
H A Dstih410.dtsi9 #include "stih410-clock.dtsi"
10 #include "stih407-family.dtsi"
11 #include "stih410-pinctrl.dtsi"
19 st,syscfg = <&syscfg_core 0x8e0>;
20 st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
22 operating-points-v2 = <&cpu0_opp_table>;
26 operating-points-v2 = <&cpu0_opp_table>;
31 compatible = "operating-points-v2";
32 opp-shared;
35 opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
[all …]
H A Dstih410.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih410-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
16 compatible = "st,stih407-usb2-phy";
17 #phy-cells = <0>;
18 st,syscfg = <&syscfg_core 0xf8 0xf4>;
21 reset-names = "global", "port";
27 compatible = "st,stih407-usb2-phy";
[all …]
/openbmc/linux/drivers/gpu/drm/sti/
H A Dsti_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <media/cec-notifier.h>
45 * @syscfg: syscfg register for pll rejection configuration
50 * @irq: hdmi interrupt number
60 * @audio_pdev: ASoC hdmi-codec platform device
70 void __iomem *syscfg; member
75 int irq; member
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
36 /* Ethernet PHY interface selection in register SYSCFG Configuration
37 *------------------------------------------
39 *------------------------------------------
41 *------------------------------------------
43 *------------------------------------------
45 *------------------------------------------
47 *------------------------------------------
63 * ---------------------------------------------------------------------------
[all …]
/openbmc/qemu/hw/arm/
H A Dstm32l4x5_soc.c4 * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
27 #include "exec/address-spaces.h"
29 #include "hw/or-irq.h"
33 #include "hw/qdev-clock.h"
46 /* Match exti line connections with their CPU IRQ number */
[all …]
H A Dstm32f205_soc.c29 #include "exec/address-spaces.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/qdev-clock.h"
55 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f205_soc_initfn()
57 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG); in stm32f205_soc_initfn()
60 object_initialize_child(obj, "usart[*]", &s->usart[i], in stm32f205_soc_initfn()
65 object_initialize_child(obj, "timer[*]", &s->timer[i], in stm32f205_soc_initfn()
69 s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); in stm32f205_soc_initfn()
72 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); in stm32f205_soc_initfn()
76 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f205_soc_initfn()
[all …]
H A Dstm32f405_soc.c27 #include "exec/address-spaces.h"
30 #include "hw/qdev-clock.h"
61 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f405_soc_initfn()
63 object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32_RCC); in stm32f405_soc_initfn()
65 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG); in stm32f405_soc_initfn()
68 object_initialize_child(obj, "usart[*]", &s->usart[i], in stm32f405_soc_initfn()
73 object_initialize_child(obj, "timer[*]", &s->timer[i], in stm32f405_soc_initfn()
78 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); in stm32f405_soc_initfn()
82 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f405_soc_initfn()
85 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI); in stm32f405_soc_initfn()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
[all …]
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
[all …]
/openbmc/qemu/include/hw/misc/
H A Dstm32f4xx_syscfg.h2 * STM32F4xx SYSCFG
39 #define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg"
56 qemu_irq irq; member
/openbmc/linux/drivers/mtd/nand/onenand/
H A Donenand_omap2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2005-2006 Nokia Corporation
8 * IRQ and DMA support written by Timo Teras
17 #include <linux/omap-gpmc.h>
21 #include <linux/dma-mapping.h>
29 #define DRIVER_NAME "omap2-onenand"
50 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id) in omap2_onenand_interrupt() argument
54 complete(&c->irq_done); in omap2_onenand_interrupt()
61 return readw(c->onenand.base + reg); in read_reg()
67 writew(value, c->onenand.base + reg); in write_reg()
[all …]
/openbmc/linux/drivers/remoteproc/
H A Dstm32_rproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/arm-smccc.h>
9 #include <linux/dma-mapping.h>
99 struct stm32_rproc *ddata = rproc->priv; in stm32_rproc_pa_to_da()
102 for (i = 0; i < ddata->nb_rmems; i++) { in stm32_rproc_pa_to_da()
103 p_mem = &ddata->rmems[i]; in stm32_rproc_pa_to_da()
105 if (pa < p_mem->bus_addr || in stm32_rproc_pa_to_da()
106 pa >= p_mem->bus_addr + p_mem->size) in stm32_rproc_pa_to_da()
108 *da = pa - p_mem->bus_addr + p_mem->dev_addr; in stm32_rproc_pa_to_da()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
[all …]
/openbmc/linux/drivers/usb/renesas_usbhs/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-1.0+
33 * +-------+ +-----------+
34 * | pipe0 |------>| fifo pio |
35 * +------------+ +-------+ +-----------+
36 * | mod_gadget |=====> | pipe1 |--+
37 * +------------+ +-------+ | +-----------+
38 * | pipe2 | | +-| fifo dma0 |
39 * +------------+ +-------+ | | +-----------+
40 * | mod_host | | pipe3 |<-|--+
41 * +------------+ +-------+ | +-----------+
[all …]
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-1.0+ */
28 #define SYSCFG 0x0000 macro
100 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
101 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
102 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
103 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
106 /* SYSCFG */
108 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
109 #define HSE (1 << 7) /* High-Speed Operation Enable */
111 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
[all …]
/openbmc/qemu/hw/misc/
H A Dstm32l4x5_syscfg.c2 * STM32L4x5 SYSCFG (System Configuration Controller)
4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
27 #include "hw/irq.h"
30 #include "hw/qdev-clock.h"
75 s->memrmp = 0x00000000; in stm32l4x5_syscfg_hold_reset()
[all …]
H A Dstm32f4xx_syscfg.c2 * STM32F4xx SYSCFG
28 #include "hw/irq.h"
36 s->syscfg_memrmp = 0x00000000; in stm32f4xx_syscfg_reset()
37 s->syscfg_pmc = 0x00000000; in stm32f4xx_syscfg_reset()
38 s->syscfg_exticr[0] = 0x00000000; in stm32f4xx_syscfg_reset()
39 s->syscfg_exticr[1] = 0x00000000; in stm32f4xx_syscfg_reset()
40 s->syscfg_exticr[2] = 0x00000000; in stm32f4xx_syscfg_reset()
41 s->syscfg_exticr[3] = 0x00000000; in stm32f4xx_syscfg_reset()
42 s->syscfg_cmpcr = 0x00000000; in stm32f4xx_syscfg_reset()
45 static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level) in stm32f4xx_syscfg_set_irq() argument
[all …]
/openbmc/qemu/include/hw/arm/
H A Dstm32l4x5_soc.h4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
29 #include "hw/or-irq.h"
37 #define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
38 #define TYPE_STM32L4X5XC_SOC "stm32l4x5xc-soc"
39 #define TYPE_STM32L4X5XE_SOC "stm32l4x5xe-soc"
[all …]

123