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/openbmc/u-boot/arch/x86/lib/
H A Dpirq_routing.c57 int i, intx; in pirq_route_irqs() local
67 for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { in pirq_route_irqs()
68 int link = irq->irq[intx].link; in pirq_route_irqs()
69 int bitmap = irq->irq[intx].bitmap; in pirq_route_irqs()
73 'A' + intx, link, bitmap); in pirq_route_irqs()
77 irq_slot[intx] = irq; in pirq_route_irqs()
94 irq_slot[intx] = irq; in pirq_route_irqs()
/openbmc/linux/Documentation/PCI/
H A Dboot-interrupts.rst20 protocol describes this in-band legacy wire-interrupt INTx mechanism for
22 describe problems with the Core IO handling of INTx message routing to the
29 When in-band legacy INTx messages are forwarded to the PCH, they in turn
103 When this bit is set. Local INTx messages received from the
110 has been to make use of PCI Interrupt pin to INTx routing tables for
112 line by default. Therefore, on chipsets where this INTx routing cannot be
147 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt
/openbmc/qemu/hw/remote/
H A Diohub.c36 int remote_iohub_map_irq(PCIDevice *pci_dev, int intx) in remote_iohub_map_irq() argument
82 int pirq, intx; in process_set_irqfd_msg() local
84 intx = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; in process_set_irqfd_msg()
86 pirq = remote_iohub_map_irq(pci_dev, intx); in process_set_irqfd_msg()
/openbmc/qemu/hw/vfio/
H A Dpci.c58 * Disabling BAR mmaping can be slow, but toggling it around INTx can
69 * other options with the x-intx-mmap-timeout-ms parameter (a value of
76 if (vdev->intx.pending) { in vfio_intx_mmap_enable()
77 timer_mod(vdev->intx.mmap_timer, in vfio_intx_mmap_enable()
78 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); in vfio_intx_mmap_enable()
89 if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) { in vfio_intx_interrupt()
93 trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin); in vfio_intx_interrupt()
95 vdev->intx.pending = true; in vfio_intx_interrupt()
98 if (vdev->intx.mmap_timeout) { in vfio_intx_interrupt()
99 timer_mod(vdev->intx.mmap_timer, in vfio_intx_interrupt()
[all …]
/openbmc/linux/drivers/net/ethernet/cisco/enic/
H A Dvnic_enet.h43 #define VENET_INTR_MODE_ANY 0 /* Try MSI-X, then MSI, then INTx */
44 #define VENET_INTR_MODE_MSI 1 /* Try MSI then INTx */
45 #define VENET_INTR_MODE_INTX 2 /* Try INTx only */
H A Denic_res.c96 c->intr_mode == VENET_INTR_MODE_INTX ? "INTx" : in enic_get_vnic_config()
252 * CQ[0 - n+m-1] point to INTR[0] for INTx, MSI in enic_init_vnic_resources()
282 * mask_on_assertion is not used for INTx due to the level- in enic_init_vnic_resources()
283 * triggered nature of INTx in enic_init_vnic_resources()
316 intr_mode == VNIC_DEV_INTR_MODE_INTX ? "legacy PCI INTx" : in enic_alloc_vnic_resources()
/openbmc/qemu/include/hw/xen/
H A Dxen-pvh-common.h29 * set_pci_intx_irq - Deliver INTX irqs to the guest.
39 * routing between INTX IRQ (0 - 3) and GSI's.
41 * @line: line the INTx line (0 => A .. 3 => B)
/openbmc/qemu/hw/isa/
H A Dlpc_ich9.c68 int intx; in ich9_cc_update_ir() local
69 for (intx = 0; intx < PCI_NUM_PINS; intx++) { in ich9_cc_update_ir()
70 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; in ich9_cc_update_ir()
101 * It is arbitrarily decided how INTx lines of PCI devices behind in ich9_cc_update()
113 int intx; in ich9_cc_init() local
125 for (intx = 0; intx < PCI_NUM_PINS; intx++) { in ich9_cc_init()
126 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; in ich9_cc_init()
276 static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) in ich9_lpc_map_irq() argument
284 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; in ich9_lpc_map_irq()
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi122 interrupt-names = "intx";
150 interrupt-names = "intx";
178 interrupt-names = "intx";
206 interrupt-names = "intx";
234 interrupt-names = "intx";
262 interrupt-names = "intx";
290 interrupt-names = "intx";
318 interrupt-names = "intx";
346 interrupt-names = "intx";
374 interrupt-names = "intx";
H A Darmada-xp-mv78260.dtsi101 interrupt-names = "intx";
129 interrupt-names = "intx";
157 interrupt-names = "intx";
185 interrupt-names = "intx";
213 interrupt-names = "intx";
241 interrupt-names = "intx";
269 interrupt-names = "intx";
297 interrupt-names = "intx";
325 interrupt-names = "intx";
H A Darmada-385.dtsi72 interrupt-names = "intx";
100 interrupt-names = "intx";
128 interrupt-names = "intx";
159 interrupt-names = "intx";
H A Darmada-xp-mv78230.dtsi86 interrupt-names = "intx";
114 interrupt-names = "intx";
142 interrupt-names = "intx";
170 interrupt-names = "intx";
198 interrupt-names = "intx";
H A Darmada-380.dtsi67 interrupt-names = "intx";
96 interrupt-names = "intx";
125 interrupt-names = "intx";
/openbmc/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c95 * The core provides a single interrupt for both INTx/MSI messages. in mobiveil_pcie_isr()
96 * So we'll read both INTx and MSI status in mobiveil_pcie_isr()
101 /* read INTx status */ in mobiveil_pcie_isr()
106 /* Handle INTx */ in mobiveil_pcie_isr()
334 .name = "mobiveil_pcie:intx",
341 /* routine to setup the INTx related data */
351 /* INTx domain operations structure */
474 /* setup INTx */ in mobiveil_pcie_init_irq_domain()
479 dev_err(dev, "Failed to get a INTx IRQ domain\n"); in mobiveil_pcie_init_irq_domain()
/openbmc/linux/drivers/net/ethernet/amd/pds_core/
H A Dcore.c109 qcq->intx == PDS_CORE_INTR_INDEX_NOT_ASSIGNED) in pdsc_qcq_intr_free()
112 pdsc_intr_free(pdsc, qcq->intx); in pdsc_qcq_intr_free()
113 qcq->intx = PDS_CORE_INTR_INDEX_NOT_ASSIGNED; in pdsc_qcq_intr_free()
122 qcq->intx = PDS_CORE_INTR_INDEX_NOT_ASSIGNED; in pdsc_qcq_intr_alloc()
131 qcq->intx = index; in pdsc_qcq_intr_alloc()
228 qcq->cq.bound_intr = &pdsc->intr_info[qcq->intx]; in pdsc_qcq_alloc()
323 cidi.intr_index = cpu_to_le16(pdsc->adminqcq.intx); in pdsc_core_init()
437 pdsc->notifyqcq.intx = pdsc->adminqcq.intx; in pdsc_setup()
495 pds_core_intr_mask(&pdsc->intr_ctrl[pdsc->adminqcq.intx], in pdsc_start()
/openbmc/qemu/hw/xen/
H A Dxen-pvh-common.c126 * We use the GPEX PCIe controller with its internal INTX PCI interrupt
127 * swizzling. This swizzling is emulated in QEMU and routes all INTX
128 * interrupts from endpoints down to only 4 INTX interrupts.
222 error_report("PCI enabled but pci-intx-irq-base not set"); in xen_pvh_init()
351 object_class_property_add(oc, "pci-intx-irq-base", "uint32_t", in xen_pvh_class_setup_common_props()
355 object_class_property_set_description(oc, "pci-intx-irq-base", in xen_pvh_class_setup_common_props()
356 "Set PCI INTX interrupt base line."); in xen_pvh_class_setup_common_props()
/openbmc/linux/drivers/scsi/csiostor/
H A Dcsio_isr.c78 * and INTx handlers.
126 * csio_fwevt_isr() - INTx wrapper for handling FW events.
209 * This routine is shared b/w MSIX and INTx.
277 * csio_scsi_intx_handler() - SCSI INTx handler
281 * This is the top level SCSI INTx handler. Calls csio_scsi_isr_handler()
295 * csio_fcoe_isr() - INTx/MSI interrupt service routine for FCoE.
329 /* Get the INTx Forward interrupt IQ. */ in csio_fcoe_isr()
556 /* Try MSIX, then MSI or fall back to INTx */ in csio_intr_enable()
580 ((hw->intr_mode == CSIO_IM_MSI) ? "MSI" : "INTx")); in csio_intr_enable()
/openbmc/linux/drivers/pci/controller/
H A Dpcie-rockchip-ep.c315 u8 intx, bool do_assert) in rockchip_pcie_ep_assert_intx() argument
319 intx &= 3; in rockchip_pcie_ep_assert_intx()
322 ep->irq_pending |= BIT(intx); in rockchip_pcie_ep_assert_intx()
328 ep->irq_pending &= ~BIT(intx); in rockchip_pcie_ep_assert_intx()
337 u8 intx) in rockchip_pcie_ep_send_legacy_irq() argument
349 * Should add some delay between toggling INTx per TRM vaguely saying in rockchip_pcie_ep_send_legacy_irq()
353 rockchip_pcie_ep_assert_intx(ep, fn, intx, true); in rockchip_pcie_ep_send_legacy_irq()
355 rockchip_pcie_ep_assert_intx(ep, fn, intx, false); in rockchip_pcie_ep_send_legacy_irq()
H A Dpcie-xilinx-cpm.c76 IMR(INTX) | \
201 .name = "INTx",
207 * xilinx_cpm_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
225 /* INTx IRQ Domain operations */
403 /* Setup INTx */ in xilinx_cpm_pcie_init_irq_domain()
471 dev_err(dev, "Failed to map INTx interrupt\n"); in xilinx_cpm_setup_irq()
475 /* Plug the INTx chained handler */ in xilinx_cpm_setup_irq()
H A Dpcie-xilinx.c202 * the respective callbacks for INTx and MSI. in xilinx_msi_top_irq_ack()
309 /* INTx Functions */
312 * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
328 /* INTx IRQ Domain operations */
462 /* Setup INTx */ in xilinx_pcie_init_irq_domain()
474 dev_err(dev, "Failed to get a INTx IRQ domain\n"); in xilinx_pcie_init_irq_domain()
/openbmc/qemu/hw/i386/xen/
H A Dxen-pvh.c64 * Deliver INTX interrupts to Xen guest.
96 * PCI INTX routing. in xen_pvh_machine_class_init()
98 * We describe the mapping between the 4 INTX interrupt and GSIs in xen_pvh_machine_class_init()
/openbmc/qemu/docs/specs/
H A Dedu.rst104 The device supports both INTx and MSI interrupt. By default, INTx is
105 used. Even if the driver disabled INTx and only uses MSI, it still
/openbmc/linux/drivers/pci/msi/
H A Dapi.c44 * free earlier allocated interrupt vectors, and restore INTx emulation.
187 * free earlier-allocated interrupt vectors, and restore INTx.
216 * * %PCI_IRQ_LEGACY Allow trying legacy INTx interrupts, if
224 * higher precedence over legacy INTx emulation.
309 * * INTx must be 0
333 * * INTx must be 0
340 * during system boot if the device is in legacy INTx mode.
/openbmc/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-ep.c319 static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx, in cdns_pcie_ep_assert_intx() argument
328 intx &= 3; in cdns_pcie_ep_assert_intx()
341 ep->irq_pending |= BIT(intx); in cdns_pcie_ep_assert_intx()
342 msg_code = MSG_CODE_ASSERT_INTA + intx; in cdns_pcie_ep_assert_intx()
344 ep->irq_pending &= ~BIT(intx); in cdns_pcie_ep_assert_intx()
345 msg_code = MSG_CODE_DEASSERT_INTA + intx; in cdns_pcie_ep_assert_intx()
363 u8 intx) in cdns_pcie_ep_send_legacy_irq() argument
371 cdns_pcie_ep_assert_intx(ep, fn, intx, true); in cdns_pcie_ep_send_legacy_irq()
376 cdns_pcie_ep_assert_intx(ep, fn, intx, false); in cdns_pcie_ep_send_legacy_irq()
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dlayerscape-pcie-gen4.txt17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.

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