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/openbmc/u-boot/arch/arm/dts/
H A Dexynos5250-pinctrl.dtsi2 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
7 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
22 #interrupt-cells = <2>;
26 gpio-controller;
27 #gpio-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
[all …]
H A Dexynos4x12-pinctrl.dtsi2 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
7 * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
22 #interrupt-cells = <2>;
26 gpio-controller;
27 #gpio-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
[all …]
H A Dexynos4210-pinctrl.dtsi2 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
4 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2011-2012 Linaro Ltd.
9 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
20 gpio-controller;
21 #gpio-cells = <2>;
23 interrupt-controller;
24 #interrupt-cells = <2>;
28 gpio-controller;
29 #gpio-cells = <2>;
[all …]
H A Dexynos54xx-pinctrl.dtsi2 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
7 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
15 #include "exynos54xx-pinctrl-uboot.dtsi"
20 gpio-controller;
21 #gpio-cells = <2>;
23 interrupt-controller;
24 #interrupt-cells = <2>;
28 gpio-controller;
29 #gpio-cells = <2>;
31 interrupt-controller;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
[all …]
H A Dexynos5260-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
[all …]
H A Dexynos5250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
[all …]
H A Dexynos5420-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpy7: gpy7-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpx0: gpx0-gpio-bank {
[all …]
/openbmc/linux/drivers/irqchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
90 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
96 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
121 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
129 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
136 tristate "Broadcom STB generic L2 interrupt controller driver"
211 bool "J-Core integrated AIC" if COMPILE_TEST
215 Support for the J-Core integrated AIC.
225 Enable support for the Renesas Interrupt Controller for external
226 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
[all …]
/openbmc/linux/arch/arm64/boot/dts/tesla/
H A Dfsd-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2021 Tesla, Inc.
11 #include "fsd-pinctrl.h"
14 gpf0: gpf0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
18 interrupt-controller;
19 #interrupt-cells = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
[all …]
H A Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
32 gpa0: gpa0-gpio-bank {
33 gpio-controller;
[all …]
H A Dexynos850-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
6 controller in some SoCs, e.g. Hisilicon SD5203.
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
[all …]
H A Dbrcm,bcm7120-l2-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
13 This interrupt controller hardware is a second level interrupt controller that
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17 Such an interrupt controller has the following hardware design:
19 - outputs multiple interrupts signals towards its interrupt controller parent
[all …]
H A Dmarvell,orion-intc.txt1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
6 - compatible: shall be "marvell,orion-intc"
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
13 - 0 maps to bit 0 of first base address,
14 - 1 maps to bit 1 of first base address,
15 - 32 maps to bit 0 of second base address, and so on.
[all …]
H A Dsamsung,exynos4210-combiner.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
[all …]
H A Dinterrupts.txt1 Specifying interrupt information for devices
4 1) Interrupt client nodes
5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
21 controller node. This property is inherited, so it may be specified in an
[all …]
H A Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Global Interrupt Controller
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
[all …]
H A Dti,pruss-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
14 to all the PRU cores. Most interrupt controllers can route 64 input events
19 remaining 8 (2 through 9) connected to external interrupt controllers
22 The property "ti,irqs-reserved" is used for denoting the connection
[all …]
H A Dmarvell,icu.txt1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
[all …]
H A Dabilis,tb10x-ictl.txt1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
15 source connected to this controller. The value shall be 2.
16 - interrupts: Specifies the list of interrupt lines which are handled by
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A D8xxx_gpio.txt3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
13 interrupt client nodes section) for details how to specify this GPIO
14 module's interrupt.
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
[all …]
H A Dgpio-mxs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MXS GPIO controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Anson Huang <Anson.Huang@nxp.com>
14 The Freescale MXS GPIO controller is part of MXS PIN controller.
16 As the GPIO controller is embedded in the PIN controller and all the
17 GPIO ports share the same IO space with PIN controller, the GPIO node
[all …]
/openbmc/linux/arch/arm64/boot/dts/st/
H A Dstm32mp251.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
13 #address-cells = <1>;
14 #size-cells = <0>;
17 compatible = "arm,cortex-a35";
20 enable-method = "psci";
24 arm-pmu {
[all …]

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