| /openbmc/linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | frontend.json | 5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct…
11 "BriefDescription": "Branch Instruction Finished",
23 "BriefDescription": "Branch Instruction completed",
47 "BriefDescription": "Number of I-ERAT reloads",
71 …ption": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
72 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
89 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
90 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
95 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
96 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
[all …]
|
| H A D | other.json | 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
23 …prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
24 …(prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)"
29 …cope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
30 …group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
35 … Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
41 …l Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
42 …s chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
47 … all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | frontend.json | 6 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
11 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al…
14 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …op-cache that holds translations of previously fetched instructions that were decoded by the legac…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
65 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
[all …]
|
| H A D | virtual-memory.json | 101 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
104 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
109 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
113 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
121 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
129 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
137 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
145 …ounts the number of page walks outstanding for an outstanding code (instruction fetch) request in …
150 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
153 … "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | frontend.json | 6 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
11 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al…
14 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …op-cache that holds translations of previously fetched instructions that were decoded by the legac…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
65 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
[all …]
|
| H A D | virtual-memory.json | 101 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
104 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
109 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
113 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
121 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
129 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
137 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
145 …ounts the number of page walks outstanding for an outstanding code (instruction fetch) request in …
150 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
153 … "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | frontend.json | 6 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
11 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al…
14 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …op-cache that holds translations of previously fetched instructions that were decoded by the legac…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
65 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
[all …]
|
| H A D | virtual-memory.json | 101 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
104 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
109 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
113 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
121 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
129 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
137 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
145 …ounts the number of page walks outstanding for an outstanding code (instruction fetch) request in …
150 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
153 … "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | frontend.json | 6 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
11 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al…
14 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …op-cache that holds translations of previously fetched instructions that were decoded by the legac…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
65 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
[all …]
|
| H A D | virtual-memory.json | 117 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
120 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
125 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
129 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
137 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
145 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
153 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
161 …ounts the number of page walks outstanding for an outstanding code (instruction fetch) request in …
166 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
169 … "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
|
| /openbmc/linux/tools/perf/pmu-events/arch/powerpc/power9/ |
| H A D | marked.json | 5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n…
15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at…
35 …ption": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflic…
65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o…
75 "BriefDescription": "Vector FP instruction completed"
80 …cription": "The processor's Instruction cache was reloaded from local core's L2 without conflict d…
85 …tion": "The processor's Instruction cache was reloaded from a location other than the local core's…
90 …ch the NTC instruction is not allowed to complete because it was interrupted by ANY exception, whi…
115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
120 …The processor's Instruction cache was reloaded from another chip's memory on the same Node or Grou…
[all …]
|
| H A D | translation.json | 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin…
50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
55 …: "Cycles during which the marked instruction is next to complete (completion is held up because t…
65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi…
75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
80 …"The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the…
100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t…
[all …]
|
| H A D | cache.json | 5 …ion": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
10 …"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of…
15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi…
20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p…
35 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and…
40 …ocessor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 …
45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its …
50 … "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group …
55 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node …
90 …"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older stor…
[all …]
|
| /openbmc/linux/sound/soc/sof/xtensa/ |
| H A D | core.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
14 #include "../sof-priv.h"
23 * From 4.4.1.5 table 4-64 Exception Causes of Xtensa
24 * Instruction Set Architecture (ISA) Reference Manual
27 {0, "IllegalInstructionCause", "Illegal instruction"},
28 {1, "SyscallCause", "SYSCALL instruction"},
30 "Processor internal physical address or data error during instruction fetch"},
34 "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"},
36 "MOVSP instruction, if caller’s registers are not in the register file"},
43 "PIF data error during instruction fetch"},
[all …]
|
| /openbmc/linux/arch/x86/include/asm/ |
| H A D | amd-ibs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include <asm/msr-index.h>
29 /* MSR 0xc0011030: IBS Fetch Control */
33 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 fetch_cnt:16, /* 16-31: instruction fetch count */
35 fetch_lat:16, /* 32-47: instruction fetch latency */
36 fetch_en:1, /* 48: instruction fetch enable */
37 fetch_val:1, /* 49: instruction fetch valid */
38 fetch_comp:1, /* 50: instruction fetch complete */
[all …]
|
| /openbmc/linux/tools/arch/x86/include/asm/ |
| H A D | amd-ibs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include "msr-index.h"
29 /* MSR 0xc0011030: IBS Fetch Control */
33 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 fetch_cnt:16, /* 16-31: instruction fetch count */
35 fetch_lat:16, /* 32-47: instruction fetch latency */
36 fetch_en:1, /* 48: instruction fetch enable */
37 fetch_val:1, /* 49: instruction fetch valid */
38 fetch_comp:1, /* 50: instruction fetch complete */
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | virtual-memory.json | 149 …"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed …
157 …"BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE…
165 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
168 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
174 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
178 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
184 …"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to …
187 …"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose a…
196 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
205 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | virtual-memory.json | 86 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
175 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
190 …"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed …
198 …he number of first level TLB misses but second level hits due to an instruction fetch that did not…
206 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
209 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
215 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
219 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
225 …"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to …
228 …"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose a…
[all …]
|
| H A D | frontend.json | 15 …-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branc…
21 "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
24 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the …
38 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
41 …op-cache that holds translations of previously fetched instructions that were decoded by the legac…
73 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
85 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
106 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
112 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
118 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | cache.json | 5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all…
11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har…
17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all…
161 …eculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access).",
173 …ption": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH…
179 …ption": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH…
185 …"BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core fo…
287 …"BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations eac…
292 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea…
316 "BriefDescription": "L2 cache requests: instruction cache reads.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | virtual-memory.json | 117 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
120 …"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and h…
125 …on": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
129 …east one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
137 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
145 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
153 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
161 …ounts the number of page walks outstanding for an outstanding code (instruction fetch) request in …
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | virtual-memory.json | 141 … "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
144 …ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
152 …tion": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it m…
157 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
164 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
168 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
176 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
184 …eted page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
192 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
200 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | virtual-memory.json | 141 … "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
144 …ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
152 …tion": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it m…
157 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
164 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
168 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
176 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
184 …eted page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
192 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
200 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | virtual-memory.json | 141 … "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
144 …ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
152 …tion": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it m…
157 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
164 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
168 …": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EP…
176 …ted page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
184 …eted page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
192 …d page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
200 …eted page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instru…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | virtual-memory.json | 70 …t during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to…
78 … to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address…
83 "BriefDescription": "Page walk completed due to an instruction fetch in a 1GB page",
86 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla…
91 "BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page",
94 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla…
99 "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page",
102 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla…
107 "BriefDescription": "Page walks outstanding due to an instruction fetch every cycle.",
110 …ion": "Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cy…
|