| /openbmc/u-boot/drivers/pinctrl/nxp/ |
| H A D | pinctrl-imx.c | 25 int mux_reg, conf_reg, input_reg; in imx_pinctrl_set_state() local
92 input_reg = pin_data[j++]; in imx_pinctrl_set_state()
98 "input_reg 0x%x, mux_mode 0x%x, " in imx_pinctrl_set_state()
100 mux_reg, conf_reg, input_reg, mux_mode, in imx_pinctrl_set_state()
145 * The input_reg[i] here is actually some in imx_pinctrl_set_state()
149 val = readl(info->base + input_reg); in imx_pinctrl_set_state()
152 writel(val, info->base + input_reg); in imx_pinctrl_set_state()
153 } else if (input_reg) { in imx_pinctrl_set_state()
162 input_reg); in imx_pinctrl_set_state()
165 info->base + input_reg); in imx_pinctrl_set_state()
[all …]
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| /openbmc/u-boot/drivers/gpio/ |
| H A D | tca642x.c | 29 { .input_reg = 0x00,
33 { .input_reg = 0x01,
37 { .input_reg = 0x02,
133 uint8_t in_reg = tca642x_regs[gpio_bank].input_reg; in tca642x_get_val()
196 tca642x_regs[i].input_reg, &data) < 0) in tca642x_info()
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| /openbmc/linux/drivers/pinctrl/freescale/ |
| H A D | pinctrl-imx.c | 217 * The input_reg[i] here is actually some IOMUXC general in imx_pmx_set_one_pin_mmio()
220 val = readl(ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
223 writel(val, ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
224 } else if (pin_mmio->input_reg) { in imx_pmx_set_one_pin_mmio()
231 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
234 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
237 pin_mmio->input_reg, pin_mmio->input_val); in imx_pmx_set_one_pin_mmio()
450 * <mux_reg conf_reg input_reg mux_mode input_val>
452 * <mux_conf_reg input_reg mux_mode input_val>
490 pin_mmio->input_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
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| H A D | pinctrl-imx.h | 24 * @input_reg: the select input register offset for this pin if any
31 u16 input_reg; member
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| /openbmc/qemu/hw/gpio/ |
| H A D | pca9552.c | 114 uint8_t input_reg = PCA9552_INPUT0 + (i / 8); in pca955x_update_pin_input() local
117 uint8_t old_value = s->regs[input_reg] & bit_mask; in pca955x_update_pin_input()
123 s->regs[input_reg] &= ~bit_mask; in pca955x_update_pin_input()
132 s->regs[input_reg] &= ~bit_mask; in pca955x_update_pin_input()
134 s->regs[input_reg] |= bit_mask; in pca955x_update_pin_input()
145 new_value = s->regs[input_reg] & bit_mask; in pca955x_update_pin_input()
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | fsl,imx93-pinctrl.yaml | 38 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
51 "input_reg" indicates the offset of select input register.
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| H A D | fsl,imx8ulp-pinctrl.yaml | 35 setting for one pin. The first 4 integers <mux_config_reg input_reg
46 "input_reg" indicates the offset of select input register.
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| H A D | fsl,imxrt1050.yaml | 36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
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| H A D | fsl,imxrt1170.yaml | 36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
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| H A D | fsl,imx8m-pinctrl.yaml | 39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
53 "input_reg" indicates the offset of select input register.
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| H A D | fsl,imx7d-pinctrl.yaml | 44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
57 "input_reg" indicates the offset of select input register.
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| H A D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| H A D | fsl,imx6ul-pinctrl.txt | 10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| H A D | fsl,imx6sll-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| H A D | fsl,imx7ulp-pinctrl.txt | 17 <mux_conf_reg input_reg mux_mode input_val> are specified
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| H A D | fsl,imx-pinctrl.txt | 26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| /openbmc/u-boot/board/ti/omap5_uevm/ |
| H A D | evm.c | 48 { .input_reg = 0x00,
52 { .input_reg = 0x00,
56 { .input_reg = 0x00,
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6ull-pinfunc-snvs.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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| H A D | imx6ull-pinfunc.h | 12 * <mux_reg conf_reg input_reg mux_mode input_val>
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| H A D | imx7ulp-pinfunc.h | 12 * <mux_conf_reg input_reg mux_mode input_val>
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | imx6ull-pinfunc-snvs.h | 13 * <mux_reg conf_reg input_reg mux_mode input_val>
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| H A D | imx6ull-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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| /openbmc/u-boot/include/ |
| H A D | tca642x.h | 54 uint8_t input_reg; member
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| /openbmc/linux/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-armada-37xx.c | 1061 u32 mask, *irq_pol, input_reg, virq, type, level; in armada_3700_pinctrl_resume() local
1066 input_reg = INPUT_VAL; in armada_3700_pinctrl_resume()
1070 input_reg = INPUT_VAL + sizeof(u32); in armada_3700_pinctrl_resume()
1086 regmap_read(info->regmap, input_reg, &level); in armada_3700_pinctrl_resume()
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| /openbmc/linux/drivers/input/touchscreen/ |
| H A D | iqs5xx.c | 901 bool input_reg = !iqs5xx->input; in fw_file_store() local
925 if (input_reg) { in fw_file_store()
|